1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 // Lowering arithmetic
6 (Add(Ptr|32|16|8) ...) => (ADDL ...)
7 (Add(32|64)F ...) => (ADDS(S|D) ...)
8 (Add32carry ...) => (ADDLcarry ...)
9 (Add32withcarry ...) => (ADCL ...)
10
11 (Sub(Ptr|32|16|8) ...) => (SUBL ...)
12 (Sub(32|64)F ...) => (SUBS(S|D) ...)
13 (Sub32carry ...) => (SUBLcarry ...)
14 (Sub32withcarry ...) => (SBBL ...)
15
16 (Mul(32|16|8) ...) => (MULL ...)
17 (Mul(32|64)F ...) => (MULS(S|D) ...)
18 (Mul32uhilo ...) => (MULLQU ...)
19
20 (Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y))
21 (Select1 (Mul32uover x y)) => (SETO (Select1 <types.TypeFlags> (MULLU x y)))
22
23 (Avg32u ...) => (AVGLU ...)
24
25 (Div(32|64)F ...) => (DIVS(S|D) ...)
26 (Div(32|32u|16|16u) ...) => (DIV(L|LU|W|WU) ...)
27 (Div8 x y) => (DIVW (SignExt8to16 x) (SignExt8to16 y))
28 (Div8u x y) => (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))
29
30 (Hmul(32|32u) ...) => (HMUL(L|LU) ...)
31
32 (Mod(32|32u|16|16u) ...) => (MOD(L|LU|W|WU) ...)
33 (Mod8 x y) => (MODW (SignExt8to16 x) (SignExt8to16 y))
34 (Mod8u x y) => (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y))
35
36 (And(32|16|8) ...) => (ANDL ...)
37 (Or(32|16|8) ...) => (ORL ...)
38 (Xor(32|16|8) ...) => (XORL ...)
39
40 (Neg(32|16|8) ...) => (NEGL ...)
41 (Neg32F x) => (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
42 (Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
43
44 (Com(32|16|8) ...) => (NOTL ...)
45
46 // Lowering boolean ops
47 (AndB ...) => (ANDL ...)
48 (OrB ...) => (ORL ...)
49 (Not x) => (XORLconst [1] x)
50
51 // Lowering pointer arithmetic
52 (OffPtr [off] ptr) => (ADDLconst [int32(off)] ptr)
53
54 (Bswap32 ...) => (BSWAPL ...)
55
56 (Sqrt ...) => (SQRTSD ...)
57 (Sqrt32 ...) => (SQRTSS ...)
58
59 (Ctz16 x) => (BSFL (ORLconst <typ.UInt32> [0x10000] x))
60 (Ctz16NonZero ...) => (BSFL ...)
61
62 // Lowering extension
63 (SignExt8to16 ...) => (MOVBLSX ...)
64 (SignExt8to32 ...) => (MOVBLSX ...)
65 (SignExt16to32 ...) => (MOVWLSX ...)
66
67 (ZeroExt8to16 ...) => (MOVBLZX ...)
68 (ZeroExt8to32 ...) => (MOVBLZX ...)
69 (ZeroExt16to32 ...) => (MOVWLZX ...)
70
71 (Signmask x) => (SARLconst x [31])
72 (Zeromask <t> x) => (XORLconst [-1] (SBBLcarrymask <t> (CMPLconst x [1])))
73 (Slicemask <t> x) => (SARLconst (NEGL <t> x) [31])
74
75 // Lowering truncation
76 // Because we ignore high parts of registers, truncates are just copies.
77 (Trunc16to8 ...) => (Copy ...)
78 (Trunc32to8 ...) => (Copy ...)
79 (Trunc32to16 ...) => (Copy ...)
80
81 // Lowering float-int conversions
82 (Cvt32to32F ...) => (CVTSL2SS ...)
83 (Cvt32to64F ...) => (CVTSL2SD ...)
84
85 (Cvt32Fto32 ...) => (CVTTSS2SL ...)
86 (Cvt64Fto32 ...) => (CVTTSD2SL ...)
87
88 (Cvt32Fto64F ...) => (CVTSS2SD ...)
89 (Cvt64Fto32F ...) => (CVTSD2SS ...)
90
91 (Round32F ...) => (Copy ...)
92 (Round64F ...) => (Copy ...)
93
94 (CvtBoolToUint8 ...) => (Copy ...)
95
96 // Lowering shifts
97 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value.
98 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff)
99 (Lsh32x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
100 (Lsh16x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
101 (Lsh8x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
102
103 (Lsh32x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y)
104 (Lsh16x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y)
105 (Lsh8x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y)
106
107 (Rsh32Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
108 (Rsh16Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [16])))
109 (Rsh8Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [8])))
110
111 (Rsh32Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRL <t> x y)
112 (Rsh16Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRW <t> x y)
113 (Rsh8Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRB <t> x y)
114
115 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value.
116 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width.
117
118 (Rsh32x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [32])))))
119 (Rsh16x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [16])))))
120 (Rsh8x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [8])))))
121
122 (Rsh32x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARL x y)
123 (Rsh16x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARW x y)
124 (Rsh8x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARB x y)
125
126 // constant shifts
127 // generic opt rewrites all constant shifts to shift by Const64
128 (Lsh32x64 x (Const64 [c])) && uint64(c) < 32 => (SHLLconst x [int32(c)])
129 (Rsh32x64 x (Const64 [c])) && uint64(c) < 32 => (SARLconst x [int32(c)])
130 (Rsh32Ux64 x (Const64 [c])) && uint64(c) < 32 => (SHRLconst x [int32(c)])
131 (Lsh16x64 x (Const64 [c])) && uint64(c) < 16 => (SHLLconst x [int32(c)])
132 (Rsh16x64 x (Const64 [c])) && uint64(c) < 16 => (SARWconst x [int16(c)])
133 (Rsh16Ux64 x (Const64 [c])) && uint64(c) < 16 => (SHRWconst x [int16(c)])
134 (Lsh8x64 x (Const64 [c])) && uint64(c) < 8 => (SHLLconst x [int32(c)])
135 (Rsh8x64 x (Const64 [c])) && uint64(c) < 8 => (SARBconst x [int8(c)])
136 (Rsh8Ux64 x (Const64 [c])) && uint64(c) < 8 => (SHRBconst x [int8(c)])
137
138 // large constant shifts
139 (Lsh32x64 _ (Const64 [c])) && uint64(c) >= 32 => (Const32 [0])
140 (Rsh32Ux64 _ (Const64 [c])) && uint64(c) >= 32 => (Const32 [0])
141 (Lsh16x64 _ (Const64 [c])) && uint64(c) >= 16 => (Const16 [0])
142 (Rsh16Ux64 _ (Const64 [c])) && uint64(c) >= 16 => (Const16 [0])
143 (Lsh8x64 _ (Const64 [c])) && uint64(c) >= 8 => (Const8 [0])
144 (Rsh8Ux64 _ (Const64 [c])) && uint64(c) >= 8 => (Const8 [0])
145
146 // large constant signed right shift, we leave the sign bit
147 (Rsh32x64 x (Const64 [c])) && uint64(c) >= 32 => (SARLconst x [31])
148 (Rsh16x64 x (Const64 [c])) && uint64(c) >= 16 => (SARWconst x [15])
149 (Rsh8x64 x (Const64 [c])) && uint64(c) >= 8 => (SARBconst x [7])
150
151 // constant rotates
152 (RotateLeft32 x (MOVLconst [c])) => (ROLLconst [c&31] x)
153 (RotateLeft16 x (MOVLconst [c])) => (ROLWconst [int16(c&15)] x)
154 (RotateLeft8 x (MOVLconst [c])) => (ROLBconst [int8(c&7)] x)
155
156 // Lowering comparisons
157 (Less32 x y) => (SETL (CMPL x y))
158 (Less16 x y) => (SETL (CMPW x y))
159 (Less8 x y) => (SETL (CMPB x y))
160 (Less32U x y) => (SETB (CMPL x y))
161 (Less16U x y) => (SETB (CMPW x y))
162 (Less8U x y) => (SETB (CMPB x y))
163 // Use SETGF with reversed operands to dodge NaN case
164 (Less64F x y) => (SETGF (UCOMISD y x))
165 (Less32F x y) => (SETGF (UCOMISS y x))
166
167 (Leq32 x y) => (SETLE (CMPL x y))
168 (Leq16 x y) => (SETLE (CMPW x y))
169 (Leq8 x y) => (SETLE (CMPB x y))
170 (Leq32U x y) => (SETBE (CMPL x y))
171 (Leq16U x y) => (SETBE (CMPW x y))
172 (Leq8U x y) => (SETBE (CMPB x y))
173 // Use SETGEF with reversed operands to dodge NaN case
174 (Leq64F x y) => (SETGEF (UCOMISD y x))
175 (Leq32F x y) => (SETGEF (UCOMISS y x))
176
177 (Eq32 x y) => (SETEQ (CMPL x y))
178 (Eq16 x y) => (SETEQ (CMPW x y))
179 (Eq8 x y) => (SETEQ (CMPB x y))
180 (EqB x y) => (SETEQ (CMPB x y))
181 (EqPtr x y) => (SETEQ (CMPL x y))
182 (Eq64F x y) => (SETEQF (UCOMISD x y))
183 (Eq32F x y) => (SETEQF (UCOMISS x y))
184
185 (Neq32 x y) => (SETNE (CMPL x y))
186 (Neq16 x y) => (SETNE (CMPW x y))
187 (Neq8 x y) => (SETNE (CMPB x y))
188 (NeqB x y) => (SETNE (CMPB x y))
189 (NeqPtr x y) => (SETNE (CMPL x y))
190 (Neq64F x y) => (SETNEF (UCOMISD x y))
191 (Neq32F x y) => (SETNEF (UCOMISS x y))
192
193 // Lowering loads
194 (Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVLload ptr mem)
195 (Load <t> ptr mem) && is16BitInt(t) => (MOVWload ptr mem)
196 (Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) => (MOVBload ptr mem)
197 (Load <t> ptr mem) && is32BitFloat(t) => (MOVSSload ptr mem)
198 (Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
199
200 // Lowering stores
201 // These more-specific FP versions of Store pattern should come first.
202 (Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVSDstore ptr val mem)
203 (Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVSSstore ptr val mem)
204
205 (Store {t} ptr val mem) && t.Size() == 4 => (MOVLstore ptr val mem)
206 (Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
207 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
208
209 // Lowering moves
210 (Move [0] _ _ mem) => mem
211 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
212 (Move [2] dst src mem) => (MOVWstore dst (MOVWload src mem) mem)
213 (Move [4] dst src mem) => (MOVLstore dst (MOVLload src mem) mem)
214 (Move [3] dst src mem) =>
215 (MOVBstore [2] dst (MOVBload [2] src mem)
216 (MOVWstore dst (MOVWload src mem) mem))
217 (Move [5] dst src mem) =>
218 (MOVBstore [4] dst (MOVBload [4] src mem)
219 (MOVLstore dst (MOVLload src mem) mem))
220 (Move [6] dst src mem) =>
221 (MOVWstore [4] dst (MOVWload [4] src mem)
222 (MOVLstore dst (MOVLload src mem) mem))
223 (Move [7] dst src mem) =>
224 (MOVLstore [3] dst (MOVLload [3] src mem)
225 (MOVLstore dst (MOVLload src mem) mem))
226 (Move [8] dst src mem) =>
227 (MOVLstore [4] dst (MOVLload [4] src mem)
228 (MOVLstore dst (MOVLload src mem) mem))
229
230 // Adjust moves to be a multiple of 4 bytes.
231 (Move [s] dst src mem)
232 && s > 8 && s%4 != 0 =>
233 (Move [s-s%4]
234 (ADDLconst <dst.Type> dst [int32(s%4)])
235 (ADDLconst <src.Type> src [int32(s%4)])
236 (MOVLstore dst (MOVLload src mem) mem))
237
238 // Medium copying uses a duff device.
239 (Move [s] dst src mem)
240 && s > 8 && s <= 4*128 && s%4 == 0
241 && !config.noDuffDevice && logLargeCopy(v, s) =>
242 (DUFFCOPY [10*(128-s/4)] dst src mem)
243 // 10 and 128 are magic constants. 10 is the number of bytes to encode:
244 // MOVL (SI), CX
245 // ADDL $4, SI
246 // MOVL CX, (DI)
247 // ADDL $4, DI
248 // and 128 is the number of such blocks. See src/runtime/duff_386.s:duffcopy.
249
250 // Large copying uses REP MOVSL.
251 (Move [s] dst src mem) && (s > 4*128 || config.noDuffDevice) && s%4 == 0 && logLargeCopy(v, s) =>
252 (REPMOVSL dst src (MOVLconst [int32(s/4)]) mem)
253
254 // Lowering Zero instructions
255 (Zero [0] _ mem) => mem
256 (Zero [1] destptr mem) => (MOVBstoreconst [0] destptr mem)
257 (Zero [2] destptr mem) => (MOVWstoreconst [0] destptr mem)
258 (Zero [4] destptr mem) => (MOVLstoreconst [0] destptr mem)
259
260 (Zero [3] destptr mem) =>
261 (MOVBstoreconst [makeValAndOff(0,2)] destptr
262 (MOVWstoreconst [makeValAndOff(0,0)] destptr mem))
263 (Zero [5] destptr mem) =>
264 (MOVBstoreconst [makeValAndOff(0,4)] destptr
265 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
266 (Zero [6] destptr mem) =>
267 (MOVWstoreconst [makeValAndOff(0,4)] destptr
268 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
269 (Zero [7] destptr mem) =>
270 (MOVLstoreconst [makeValAndOff(0,3)] destptr
271 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
272
273 // Strip off any fractional word zeroing.
274 (Zero [s] destptr mem) && s%4 != 0 && s > 4 =>
275 (Zero [s-s%4] (ADDLconst destptr [int32(s%4)])
276 (MOVLstoreconst [0] destptr mem))
277
278 // Zero small numbers of words directly.
279 (Zero [8] destptr mem) =>
280 (MOVLstoreconst [makeValAndOff(0,4)] destptr
281 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
282 (Zero [12] destptr mem) =>
283 (MOVLstoreconst [makeValAndOff(0,8)] destptr
284 (MOVLstoreconst [makeValAndOff(0,4)] destptr
285 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)))
286 (Zero [16] destptr mem) =>
287 (MOVLstoreconst [makeValAndOff(0,12)] destptr
288 (MOVLstoreconst [makeValAndOff(0,8)] destptr
289 (MOVLstoreconst [makeValAndOff(0,4)] destptr
290 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))))
291
292 // Medium zeroing uses a duff device.
293 (Zero [s] destptr mem)
294 && s > 16 && s <= 4*128 && s%4 == 0
295 && !config.noDuffDevice =>
296 (DUFFZERO [1*(128-s/4)] destptr (MOVLconst [0]) mem)
297 // 1 and 128 are magic constants. 1 is the number of bytes to encode STOSL.
298 // 128 is the number of STOSL instructions in duffzero.
299 // See src/runtime/duff_386.s:duffzero.
300
301 // Large zeroing uses REP STOSQ.
302 (Zero [s] destptr mem)
303 && (s > 4*128 || (config.noDuffDevice && s > 16))
304 && s%4 == 0 =>
305 (REPSTOSL destptr (MOVLconst [int32(s/4)]) (MOVLconst [0]) mem)
306
307
308 // Lowering constants
309 (Const8 [c]) => (MOVLconst [int32(c)])
310 (Const16 [c]) => (MOVLconst [int32(c)])
311 (Const32 ...) => (MOVLconst ...)
312 (Const(32|64)F ...) => (MOVS(S|D)const ...)
313 (ConstNil) => (MOVLconst [0])
314 (ConstBool [c]) => (MOVLconst [b2i32(c)])
315
316 // Lowering calls
317 (StaticCall ...) => (CALLstatic ...)
318 (ClosureCall ...) => (CALLclosure ...)
319 (InterCall ...) => (CALLinter ...)
320 (TailCall ...) => (CALLtail ...)
321
322 // Miscellaneous
323 (IsNonNil p) => (SETNE (TESTL p p))
324 (IsInBounds idx len) => (SETB (CMPL idx len))
325 (IsSliceInBounds idx len) => (SETBE (CMPL idx len))
326 (NilCheck ...) => (LoweredNilCheck ...)
327 (GetG ...) => (LoweredGetG ...)
328 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
329 (GetCallerPC ...) => (LoweredGetCallerPC ...)
330 (GetCallerSP ...) => (LoweredGetCallerSP ...)
331 (Addr {sym} base) => (LEAL {sym} base)
332 (LocalAddr {sym} base _) => (LEAL {sym} base)
333
334 // block rewrites
335 (If (SETL cmp) yes no) => (LT cmp yes no)
336 (If (SETLE cmp) yes no) => (LE cmp yes no)
337 (If (SETG cmp) yes no) => (GT cmp yes no)
338 (If (SETGE cmp) yes no) => (GE cmp yes no)
339 (If (SETEQ cmp) yes no) => (EQ cmp yes no)
340 (If (SETNE cmp) yes no) => (NE cmp yes no)
341 (If (SETB cmp) yes no) => (ULT cmp yes no)
342 (If (SETBE cmp) yes no) => (ULE cmp yes no)
343 (If (SETA cmp) yes no) => (UGT cmp yes no)
344 (If (SETAE cmp) yes no) => (UGE cmp yes no)
345 (If (SETO cmp) yes no) => (OS cmp yes no)
346
347 // Special case for floating point - LF/LEF not generated
348 (If (SETGF cmp) yes no) => (UGT cmp yes no)
349 (If (SETGEF cmp) yes no) => (UGE cmp yes no)
350 (If (SETEQF cmp) yes no) => (EQF cmp yes no)
351 (If (SETNEF cmp) yes no) => (NEF cmp yes no)
352
353 (If cond yes no) => (NE (TESTB cond cond) yes no)
354
355 // Write barrier.
356 (WB ...) => (LoweredWB ...)
357
358 (PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
359 (PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
360 (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
361
362 (PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 0 => (LoweredPanicExtendA [kind] hi lo y mem)
363 (PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 1 => (LoweredPanicExtendB [kind] hi lo y mem)
364 (PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 => (LoweredPanicExtendC [kind] hi lo y mem)
365
366 // ***************************
367 // Above: lowering rules
368 // Below: optimizations
369 // ***************************
370 // TODO: Should the optimizations be a separate pass?
371
372 // Fold boolean tests into blocks
373 (NE (TESTB (SETL cmp) (SETL cmp)) yes no) => (LT cmp yes no)
374 (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE cmp yes no)
375 (NE (TESTB (SETG cmp) (SETG cmp)) yes no) => (GT cmp yes no)
376 (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE cmp yes no)
377 (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ cmp yes no)
378 (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE cmp yes no)
379 (NE (TESTB (SETB cmp) (SETB cmp)) yes no) => (ULT cmp yes no)
380 (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) => (ULE cmp yes no)
381 (NE (TESTB (SETA cmp) (SETA cmp)) yes no) => (UGT cmp yes no)
382 (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) => (UGE cmp yes no)
383 (NE (TESTB (SETO cmp) (SETO cmp)) yes no) => (OS cmp yes no)
384
385 // Special case for floating point - LF/LEF not generated
386 (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) => (UGT cmp yes no)
387 (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) => (UGE cmp yes no)
388 (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) => (EQF cmp yes no)
389 (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) => (NEF cmp yes no)
390
391 // fold constants into instructions
392 (ADDL x (MOVLconst [c])) => (ADDLconst [c] x)
393 (ADDLcarry x (MOVLconst [c])) => (ADDLconstcarry [c] x)
394 (ADCL x (MOVLconst [c]) f) => (ADCLconst [c] x f)
395
396 (SUBL x (MOVLconst [c])) => (SUBLconst x [c])
397 (SUBL (MOVLconst [c]) x) => (NEGL (SUBLconst <v.Type> x [c]))
398 (SUBLcarry x (MOVLconst [c])) => (SUBLconstcarry [c] x)
399 (SBBL x (MOVLconst [c]) f) => (SBBLconst [c] x f)
400
401 (MULL x (MOVLconst [c])) => (MULLconst [c] x)
402 (ANDL x (MOVLconst [c])) => (ANDLconst [c] x)
403
404 (ANDLconst [c] (ANDLconst [d] x)) => (ANDLconst [c & d] x)
405 (XORLconst [c] (XORLconst [d] x)) => (XORLconst [c ^ d] x)
406 (MULLconst [c] (MULLconst [d] x)) => (MULLconst [c * d] x)
407
408 (ORL x (MOVLconst [c])) => (ORLconst [c] x)
409 (XORL x (MOVLconst [c])) => (XORLconst [c] x)
410
411 (SHLL x (MOVLconst [c])) => (SHLLconst [c&31] x)
412 (SHRL x (MOVLconst [c])) => (SHRLconst [c&31] x)
413 (SHRW x (MOVLconst [c])) && c&31 < 16 => (SHRWconst [int16(c&31)] x)
414 (SHRW _ (MOVLconst [c])) && c&31 >= 16 => (MOVLconst [0])
415 (SHRB x (MOVLconst [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x)
416 (SHRB _ (MOVLconst [c])) && c&31 >= 8 => (MOVLconst [0])
417
418 (SARL x (MOVLconst [c])) => (SARLconst [c&31] x)
419 (SARW x (MOVLconst [c])) => (SARWconst [int16(min(int64(c&31),15))] x)
420 (SARB x (MOVLconst [c])) => (SARBconst [int8(min(int64(c&31),7))] x)
421
422 (SARL x (ANDLconst [31] y)) => (SARL x y)
423 (SHLL x (ANDLconst [31] y)) => (SHLL x y)
424 (SHRL x (ANDLconst [31] y)) => (SHRL x y)
425
426 // Rotate instructions
427
428 (ADDL (SHLLconst [c] x) (SHRLconst [d] x)) && d == 32-c => (ROLLconst [c] x)
429 ( ORL (SHLLconst [c] x) (SHRLconst [d] x)) && d == 32-c => (ROLLconst [c] x)
430 (XORL (SHLLconst [c] x) (SHRLconst [d] x)) && d == 32-c => (ROLLconst [c] x)
431
432 (ADDL <t> (SHLLconst x [c]) (SHRWconst x [d])) && c < 16 && d == int16(16-c) && t.Size() == 2
433 => (ROLWconst x [int16(c)])
434 ( ORL <t> (SHLLconst x [c]) (SHRWconst x [d])) && c < 16 && d == int16(16-c) && t.Size() == 2
435 => (ROLWconst x [int16(c)])
436 (XORL <t> (SHLLconst x [c]) (SHRWconst x [d])) && c < 16 && d == int16(16-c) && t.Size() == 2
437 => (ROLWconst x [int16(c)])
438
439 (ADDL <t> (SHLLconst x [c]) (SHRBconst x [d])) && c < 8 && d == int8(8-c) && t.Size() == 1
440 => (ROLBconst x [int8(c)])
441 ( ORL <t> (SHLLconst x [c]) (SHRBconst x [d])) && c < 8 && d == int8(8-c) && t.Size() == 1
442 => (ROLBconst x [int8(c)])
443 (XORL <t> (SHLLconst x [c]) (SHRBconst x [d])) && c < 8 && d == int8(8-c) && t.Size() == 1
444 => (ROLBconst x [int8(c)])
445
446 (ROLLconst [c] (ROLLconst [d] x)) => (ROLLconst [(c+d)&31] x)
447 (ROLWconst [c] (ROLWconst [d] x)) => (ROLWconst [(c+d)&15] x)
448 (ROLBconst [c] (ROLBconst [d] x)) => (ROLBconst [(c+d)& 7] x)
449
450
451 // Constant shift simplifications
452
453 (SHLLconst x [0]) => x
454 (SHRLconst x [0]) => x
455 (SARLconst x [0]) => x
456
457 (SHRWconst x [0]) => x
458 (SARWconst x [0]) => x
459
460 (SHRBconst x [0]) => x
461 (SARBconst x [0]) => x
462
463 (ROLLconst [0] x) => x
464 (ROLWconst [0] x) => x
465 (ROLBconst [0] x) => x
466
467 // Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits)
468 // because the x86 instructions are defined to use all 5 bits of the shift even
469 // for the small shifts. I don't think we'll ever generate a weird shift (e.g.
470 // (SHRW x (MOVLconst [24])), but just in case.
471
472 (CMPL x (MOVLconst [c])) => (CMPLconst x [c])
473 (CMPL (MOVLconst [c]) x) => (InvertFlags (CMPLconst x [c]))
474 (CMPW x (MOVLconst [c])) => (CMPWconst x [int16(c)])
475 (CMPW (MOVLconst [c]) x) => (InvertFlags (CMPWconst x [int16(c)]))
476 (CMPB x (MOVLconst [c])) => (CMPBconst x [int8(c)])
477 (CMPB (MOVLconst [c]) x) => (InvertFlags (CMPBconst x [int8(c)]))
478
479 // Canonicalize the order of arguments to comparisons - helps with CSE.
480 (CMP(L|W|B) x y) && canonLessThan(x,y) => (InvertFlags (CMP(L|W|B) y x))
481
482 // strength reduction
483 // Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf:
484 // 1 - addl, shll, leal, negl, subl
485 // 3 - imull
486 // This limits the rewrites to two instructions.
487 // Note that negl always operates in-place,
488 // which can require a register-register move
489 // to preserve the original value,
490 // so it must be used with care.
491 (MULLconst [-9] x) => (NEGL (LEAL8 <v.Type> x x))
492 (MULLconst [-5] x) => (NEGL (LEAL4 <v.Type> x x))
493 (MULLconst [-3] x) => (NEGL (LEAL2 <v.Type> x x))
494 (MULLconst [-1] x) => (NEGL x)
495 (MULLconst [0] _) => (MOVLconst [0])
496 (MULLconst [1] x) => x
497 (MULLconst [3] x) => (LEAL2 x x)
498 (MULLconst [5] x) => (LEAL4 x x)
499 (MULLconst [7] x) => (LEAL2 x (LEAL2 <v.Type> x x))
500 (MULLconst [9] x) => (LEAL8 x x)
501 (MULLconst [11] x) => (LEAL2 x (LEAL4 <v.Type> x x))
502 (MULLconst [13] x) => (LEAL4 x (LEAL2 <v.Type> x x))
503 (MULLconst [19] x) => (LEAL2 x (LEAL8 <v.Type> x x))
504 (MULLconst [21] x) => (LEAL4 x (LEAL4 <v.Type> x x))
505 (MULLconst [25] x) => (LEAL8 x (LEAL2 <v.Type> x x))
506 (MULLconst [27] x) => (LEAL8 (LEAL2 <v.Type> x x) (LEAL2 <v.Type> x x))
507 (MULLconst [37] x) => (LEAL4 x (LEAL8 <v.Type> x x))
508 (MULLconst [41] x) => (LEAL8 x (LEAL4 <v.Type> x x))
509 (MULLconst [45] x) => (LEAL8 (LEAL4 <v.Type> x x) (LEAL4 <v.Type> x x))
510 (MULLconst [73] x) => (LEAL8 x (LEAL8 <v.Type> x x))
511 (MULLconst [81] x) => (LEAL8 (LEAL8 <v.Type> x x) (LEAL8 <v.Type> x x))
512
513 (MULLconst [c] x) && isPowerOfTwo32(c+1) && c >= 15 => (SUBL (SHLLconst <v.Type> [int32(log32(c+1))] x) x)
514 (MULLconst [c] x) && isPowerOfTwo32(c-1) && c >= 17 => (LEAL1 (SHLLconst <v.Type> [int32(log32(c-1))] x) x)
515 (MULLconst [c] x) && isPowerOfTwo32(c-2) && c >= 34 => (LEAL2 (SHLLconst <v.Type> [int32(log32(c-2))] x) x)
516 (MULLconst [c] x) && isPowerOfTwo32(c-4) && c >= 68 => (LEAL4 (SHLLconst <v.Type> [int32(log32(c-4))] x) x)
517 (MULLconst [c] x) && isPowerOfTwo32(c-8) && c >= 136 => (LEAL8 (SHLLconst <v.Type> [int32(log32(c-8))] x) x)
518 (MULLconst [c] x) && c%3 == 0 && isPowerOfTwo32(c/3) => (SHLLconst [int32(log32(c/3))] (LEAL2 <v.Type> x x))
519 (MULLconst [c] x) && c%5 == 0 && isPowerOfTwo32(c/5) => (SHLLconst [int32(log32(c/5))] (LEAL4 <v.Type> x x))
520 (MULLconst [c] x) && c%9 == 0 && isPowerOfTwo32(c/9) => (SHLLconst [int32(log32(c/9))] (LEAL8 <v.Type> x x))
521
522 // combine add/shift into LEAL
523 (ADDL x (SHLLconst [3] y)) => (LEAL8 x y)
524 (ADDL x (SHLLconst [2] y)) => (LEAL4 x y)
525 (ADDL x (SHLLconst [1] y)) => (LEAL2 x y)
526 (ADDL x (ADDL y y)) => (LEAL2 x y)
527 (ADDL x (ADDL x y)) => (LEAL2 y x)
528
529 // combine ADDL/ADDLconst into LEAL1
530 (ADDLconst [c] (ADDL x y)) => (LEAL1 [c] x y)
531 (ADDL (ADDLconst [c] x) y) => (LEAL1 [c] x y)
532
533 // fold ADDL into LEAL
534 (ADDLconst [c] (LEAL [d] {s} x)) && is32Bit(int64(c)+int64(d)) => (LEAL [c+d] {s} x)
535 (LEAL [c] {s} (ADDLconst [d] x)) && is32Bit(int64(c)+int64(d)) => (LEAL [c+d] {s} x)
536 (ADDLconst [c] x:(SP)) => (LEAL [c] x) // so it is rematerializeable
537 (LEAL [c] {s} (ADDL x y)) && x.Op != OpSB && y.Op != OpSB => (LEAL1 [c] {s} x y)
538 (ADDL x (LEAL [c] {s} y)) && x.Op != OpSB && y.Op != OpSB => (LEAL1 [c] {s} x y)
539
540 // fold ADDLconst into LEALx
541 (ADDLconst [c] (LEAL1 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL1 [c+d] {s} x y)
542 (ADDLconst [c] (LEAL2 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL2 [c+d] {s} x y)
543 (ADDLconst [c] (LEAL4 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL4 [c+d] {s} x y)
544 (ADDLconst [c] (LEAL8 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL8 [c+d] {s} x y)
545 (LEAL1 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL1 [c+d] {s} x y)
546 (LEAL2 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL2 [c+d] {s} x y)
547 (LEAL2 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB => (LEAL2 [c+2*d] {s} x y)
548 (LEAL4 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL4 [c+d] {s} x y)
549 (LEAL4 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB => (LEAL4 [c+4*d] {s} x y)
550 (LEAL8 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL8 [c+d] {s} x y)
551 (LEAL8 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB => (LEAL8 [c+8*d] {s} x y)
552
553 // fold shifts into LEALx
554 (LEAL1 [c] {s} x (SHLLconst [1] y)) => (LEAL2 [c] {s} x y)
555 (LEAL1 [c] {s} x (SHLLconst [2] y)) => (LEAL4 [c] {s} x y)
556 (LEAL1 [c] {s} x (SHLLconst [3] y)) => (LEAL8 [c] {s} x y)
557 (LEAL2 [c] {s} x (SHLLconst [1] y)) => (LEAL4 [c] {s} x y)
558 (LEAL2 [c] {s} x (SHLLconst [2] y)) => (LEAL8 [c] {s} x y)
559 (LEAL4 [c] {s} x (SHLLconst [1] y)) => (LEAL8 [c] {s} x y)
560
561 // reverse ordering of compare instruction
562 (SETL (InvertFlags x)) => (SETG x)
563 (SETG (InvertFlags x)) => (SETL x)
564 (SETB (InvertFlags x)) => (SETA x)
565 (SETA (InvertFlags x)) => (SETB x)
566 (SETLE (InvertFlags x)) => (SETGE x)
567 (SETGE (InvertFlags x)) => (SETLE x)
568 (SETBE (InvertFlags x)) => (SETAE x)
569 (SETAE (InvertFlags x)) => (SETBE x)
570 (SETEQ (InvertFlags x)) => (SETEQ x)
571 (SETNE (InvertFlags x)) => (SETNE x)
572
573 // sign extended loads
574 // Note: The combined instruction must end up in the same block
575 // as the original load. If not, we end up making a value with
576 // memory type live in two different blocks, which can lead to
577 // multiple memory values alive simultaneously.
578 // Make sure we don't combine these ops if the load has another use.
579 // This prevents a single load from being split into multiple loads
580 // which then might return different values. See test/atomicload.go.
581 (MOVBLSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBLSXload <v.Type> [off] {sym} ptr mem)
582 (MOVBLZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
583 (MOVWLSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWLSXload <v.Type> [off] {sym} ptr mem)
584 (MOVWLZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
585
586 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
587 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBLZX x)
588 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWLZX x)
589 (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
590 (MOVBLSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBLSX x)
591 (MOVWLSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWLSX x)
592
593 // Fold extensions and ANDs together.
594 (MOVBLZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x)
595 (MOVWLZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x)
596 (MOVBLSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x)
597 (MOVWLSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x)
598
599 // Don't extend before storing
600 (MOVWstore [off] {sym} ptr (MOVWL(S|Z)X x) mem) => (MOVWstore [off] {sym} ptr x mem)
601 (MOVBstore [off] {sym} ptr (MOVBL(S|Z)X x) mem) => (MOVBstore [off] {sym} ptr x mem)
602
603 // fold constants into memory operations
604 // Note that this is not always a good idea because if not all the uses of
605 // the ADDLconst get eliminated, we still have to compute the ADDLconst and we now
606 // have potentially two live values (ptr and (ADDLconst [off] ptr)) instead of one.
607 // Nevertheless, let's do it!
608 (MOV(L|W|B|SS|SD)load [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
609 (MOV(L|W|B|SS|SD)load [off1+off2] {sym} ptr mem)
610 (MOV(L|W|B|SS|SD)store [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(int64(off1)+int64(off2)) =>
611 (MOV(L|W|B|SS|SD)store [off1+off2] {sym} ptr val mem)
612
613 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
614 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
615 ((ADD|SUB|MUL|DIV)SSload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
616 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {sym} val base mem)
617 ((ADD|SUB|MUL|DIV)SDload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
618 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {sym} val base mem)
619 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDLconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
620 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem)
621 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) && valoff1.canAdd32(off2) =>
622 ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {sym} base mem)
623
624 // Fold constants into stores.
625 (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) =>
626 (MOVLstoreconst [makeValAndOff(c,off)] {sym} ptr mem)
627 (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) =>
628 (MOVWstoreconst [makeValAndOff(c,off)] {sym} ptr mem)
629 (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) =>
630 (MOVBstoreconst [makeValAndOff(c,off)] {sym} ptr mem)
631
632 // Fold address offsets into constant stores.
633 (MOV(L|W|B)storeconst [sc] {s} (ADDLconst [off] ptr) mem) && sc.canAdd32(off) =>
634 (MOV(L|W|B)storeconst [sc.addOffset32(off)] {s} ptr mem)
635
636 // We need to fold LEAL into the MOVx ops so that the live variable analysis knows
637 // what variables are being read/written by the ops.
638 // Note: we turn off this merging for operations on globals when building
639 // position-independent code (when Flag_shared is set).
640 // PIC needs a spare register to load the PC into. Having the LEAL be
641 // a separate instruction gives us that register. Having the LEAL be
642 // a separate instruction also allows it to be CSEd (which is good because
643 // it compiles to a thunk call).
644 (MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
645 && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
646 (MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1+off2] {mergeSym(sym1,sym2)} base mem)
647
648 (MOV(L|W|B|SS|SD)store [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
649 && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
650 (MOV(L|W|B|SS|SD)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
651
652 (MOV(L|W|B)storeconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off)
653 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
654 (MOV(L|W|B)storeconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem)
655
656 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
657 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
658 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
659 ((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
660 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
661 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
662 ((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
663 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
664 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
665 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
666 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
667 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
668 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
669 && valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
670 ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
671
672 // Merge load/store to op
673 ((ADD|AND|OR|XOR|SUB|MUL)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|AND|OR|XOR|SUB|MUL)Lload x [off] {sym} ptr mem)
674 ((ADD|SUB|MUL|DIV)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SDload x [off] {sym} ptr mem)
675 ((ADD|SUB|MUL|DIV)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SSload x [off] {sym} ptr mem)
676 (MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) => ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
677 (MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
678 ((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
679 (MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
680 && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
681 ((ADD|AND|OR|XOR)Lconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
682
683 // fold LEALs together
684 (LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
685 (LEAL [off1+off2] {mergeSym(sym1,sym2)} x)
686
687 // LEAL into LEAL1
688 (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
689 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
690
691 // LEAL1 into LEAL
692 (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
693 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
694
695 // LEAL into LEAL[248]
696 (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
697 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
698 (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
699 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
700 (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
701 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
702
703 // LEAL[248] into LEAL
704 (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
705 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
706 (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
707 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
708 (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
709 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
710
711 // LEAL[1248] into LEAL[1248]. Only some such merges are possible.
712 (LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} y y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
713 (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} x y)
714 (LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
715 (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} y x)
716 (LEAL2 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+2*int64(off2)) =>
717 (LEAL4 [off1+2*off2] {sym} x y)
718 (LEAL4 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+4*int64(off2)) =>
719 (LEAL8 [off1+4*off2] {sym} x y)
720
721 // Absorb InvertFlags into branches.
722 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
723 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
724 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
725 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
726 (ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
727 (UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
728 (ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
729 (UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
730 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
731 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
732
733 // Constant comparisons.
734 (CMPLconst (MOVLconst [x]) [y]) && x==y => (FlagEQ)
735 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)<uint32(y) => (FlagLT_ULT)
736 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)>uint32(y) => (FlagLT_UGT)
737 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)<uint32(y) => (FlagGT_ULT)
738 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)>uint32(y) => (FlagGT_UGT)
739
740 (CMPWconst (MOVLconst [x]) [y]) && int16(x)==y => (FlagEQ)
741 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)<uint16(y) => (FlagLT_ULT)
742 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)>uint16(y) => (FlagLT_UGT)
743 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)<uint16(y) => (FlagGT_ULT)
744 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)>uint16(y) => (FlagGT_UGT)
745
746 (CMPBconst (MOVLconst [x]) [y]) && int8(x)==y => (FlagEQ)
747 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)<uint8(y) => (FlagLT_ULT)
748 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)>uint8(y) => (FlagLT_UGT)
749 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)<uint8(y) => (FlagGT_ULT)
750 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)>uint8(y) => (FlagGT_UGT)
751
752 // Other known comparisons.
753 (CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) => (FlagLT_ULT)
754 (CMPLconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
755 (CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < n => (FlagLT_ULT)
756 (CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < n => (FlagLT_ULT)
757 // TODO: DIVxU also.
758
759 // Absorb flag constants into SBB ops.
760 (SBBLcarrymask (FlagEQ)) => (MOVLconst [0])
761 (SBBLcarrymask (FlagLT_ULT)) => (MOVLconst [-1])
762 (SBBLcarrymask (FlagLT_UGT)) => (MOVLconst [0])
763 (SBBLcarrymask (FlagGT_ULT)) => (MOVLconst [-1])
764 (SBBLcarrymask (FlagGT_UGT)) => (MOVLconst [0])
765
766 // Absorb flag constants into branches.
767 (EQ (FlagEQ) yes no) => (First yes no)
768 (EQ (FlagLT_ULT) yes no) => (First no yes)
769 (EQ (FlagLT_UGT) yes no) => (First no yes)
770 (EQ (FlagGT_ULT) yes no) => (First no yes)
771 (EQ (FlagGT_UGT) yes no) => (First no yes)
772
773 (NE (FlagEQ) yes no) => (First no yes)
774 (NE (FlagLT_ULT) yes no) => (First yes no)
775 (NE (FlagLT_UGT) yes no) => (First yes no)
776 (NE (FlagGT_ULT) yes no) => (First yes no)
777 (NE (FlagGT_UGT) yes no) => (First yes no)
778
779 (LT (FlagEQ) yes no) => (First no yes)
780 (LT (FlagLT_ULT) yes no) => (First yes no)
781 (LT (FlagLT_UGT) yes no) => (First yes no)
782 (LT (FlagGT_ULT) yes no) => (First no yes)
783 (LT (FlagGT_UGT) yes no) => (First no yes)
784
785 (LE (FlagEQ) yes no) => (First yes no)
786 (LE (FlagLT_ULT) yes no) => (First yes no)
787 (LE (FlagLT_UGT) yes no) => (First yes no)
788 (LE (FlagGT_ULT) yes no) => (First no yes)
789 (LE (FlagGT_UGT) yes no) => (First no yes)
790
791 (GT (FlagEQ) yes no) => (First no yes)
792 (GT (FlagLT_ULT) yes no) => (First no yes)
793 (GT (FlagLT_UGT) yes no) => (First no yes)
794 (GT (FlagGT_ULT) yes no) => (First yes no)
795 (GT (FlagGT_UGT) yes no) => (First yes no)
796
797 (GE (FlagEQ) yes no) => (First yes no)
798 (GE (FlagLT_ULT) yes no) => (First no yes)
799 (GE (FlagLT_UGT) yes no) => (First no yes)
800 (GE (FlagGT_ULT) yes no) => (First yes no)
801 (GE (FlagGT_UGT) yes no) => (First yes no)
802
803 (ULT (FlagEQ) yes no) => (First no yes)
804 (ULT (FlagLT_ULT) yes no) => (First yes no)
805 (ULT (FlagLT_UGT) yes no) => (First no yes)
806 (ULT (FlagGT_ULT) yes no) => (First yes no)
807 (ULT (FlagGT_UGT) yes no) => (First no yes)
808
809 (ULE (FlagEQ) yes no) => (First yes no)
810 (ULE (FlagLT_ULT) yes no) => (First yes no)
811 (ULE (FlagLT_UGT) yes no) => (First no yes)
812 (ULE (FlagGT_ULT) yes no) => (First yes no)
813 (ULE (FlagGT_UGT) yes no) => (First no yes)
814
815 (UGT (FlagEQ) yes no) => (First no yes)
816 (UGT (FlagLT_ULT) yes no) => (First no yes)
817 (UGT (FlagLT_UGT) yes no) => (First yes no)
818 (UGT (FlagGT_ULT) yes no) => (First no yes)
819 (UGT (FlagGT_UGT) yes no) => (First yes no)
820
821 (UGE (FlagEQ) yes no) => (First yes no)
822 (UGE (FlagLT_ULT) yes no) => (First no yes)
823 (UGE (FlagLT_UGT) yes no) => (First yes no)
824 (UGE (FlagGT_ULT) yes no) => (First no yes)
825 (UGE (FlagGT_UGT) yes no) => (First yes no)
826
827 // Absorb flag constants into SETxx ops.
828 (SETEQ (FlagEQ)) => (MOVLconst [1])
829 (SETEQ (FlagLT_ULT)) => (MOVLconst [0])
830 (SETEQ (FlagLT_UGT)) => (MOVLconst [0])
831 (SETEQ (FlagGT_ULT)) => (MOVLconst [0])
832 (SETEQ (FlagGT_UGT)) => (MOVLconst [0])
833
834 (SETNE (FlagEQ)) => (MOVLconst [0])
835 (SETNE (FlagLT_ULT)) => (MOVLconst [1])
836 (SETNE (FlagLT_UGT)) => (MOVLconst [1])
837 (SETNE (FlagGT_ULT)) => (MOVLconst [1])
838 (SETNE (FlagGT_UGT)) => (MOVLconst [1])
839
840 (SETL (FlagEQ)) => (MOVLconst [0])
841 (SETL (FlagLT_ULT)) => (MOVLconst [1])
842 (SETL (FlagLT_UGT)) => (MOVLconst [1])
843 (SETL (FlagGT_ULT)) => (MOVLconst [0])
844 (SETL (FlagGT_UGT)) => (MOVLconst [0])
845
846 (SETLE (FlagEQ)) => (MOVLconst [1])
847 (SETLE (FlagLT_ULT)) => (MOVLconst [1])
848 (SETLE (FlagLT_UGT)) => (MOVLconst [1])
849 (SETLE (FlagGT_ULT)) => (MOVLconst [0])
850 (SETLE (FlagGT_UGT)) => (MOVLconst [0])
851
852 (SETG (FlagEQ)) => (MOVLconst [0])
853 (SETG (FlagLT_ULT)) => (MOVLconst [0])
854 (SETG (FlagLT_UGT)) => (MOVLconst [0])
855 (SETG (FlagGT_ULT)) => (MOVLconst [1])
856 (SETG (FlagGT_UGT)) => (MOVLconst [1])
857
858 (SETGE (FlagEQ)) => (MOVLconst [1])
859 (SETGE (FlagLT_ULT)) => (MOVLconst [0])
860 (SETGE (FlagLT_UGT)) => (MOVLconst [0])
861 (SETGE (FlagGT_ULT)) => (MOVLconst [1])
862 (SETGE (FlagGT_UGT)) => (MOVLconst [1])
863
864 (SETB (FlagEQ)) => (MOVLconst [0])
865 (SETB (FlagLT_ULT)) => (MOVLconst [1])
866 (SETB (FlagLT_UGT)) => (MOVLconst [0])
867 (SETB (FlagGT_ULT)) => (MOVLconst [1])
868 (SETB (FlagGT_UGT)) => (MOVLconst [0])
869
870 (SETBE (FlagEQ)) => (MOVLconst [1])
871 (SETBE (FlagLT_ULT)) => (MOVLconst [1])
872 (SETBE (FlagLT_UGT)) => (MOVLconst [0])
873 (SETBE (FlagGT_ULT)) => (MOVLconst [1])
874 (SETBE (FlagGT_UGT)) => (MOVLconst [0])
875
876 (SETA (FlagEQ)) => (MOVLconst [0])
877 (SETA (FlagLT_ULT)) => (MOVLconst [0])
878 (SETA (FlagLT_UGT)) => (MOVLconst [1])
879 (SETA (FlagGT_ULT)) => (MOVLconst [0])
880 (SETA (FlagGT_UGT)) => (MOVLconst [1])
881
882 (SETAE (FlagEQ)) => (MOVLconst [1])
883 (SETAE (FlagLT_ULT)) => (MOVLconst [0])
884 (SETAE (FlagLT_UGT)) => (MOVLconst [1])
885 (SETAE (FlagGT_ULT)) => (MOVLconst [0])
886 (SETAE (FlagGT_UGT)) => (MOVLconst [1])
887
888 // Remove redundant *const ops
889 (ADDLconst [c] x) && c==0 => x
890 (SUBLconst [c] x) && c==0 => x
891 (ANDLconst [c] _) && c==0 => (MOVLconst [0])
892 (ANDLconst [c] x) && c==-1 => x
893 (ORLconst [c] x) && c==0 => x
894 (ORLconst [c] _) && c==-1 => (MOVLconst [-1])
895 (XORLconst [c] x) && c==0 => x
896 // TODO: since we got rid of the W/B versions, we might miss
897 // things like (ANDLconst [0x100] x) which were formerly
898 // (ANDBconst [0] x). Probably doesn't happen very often.
899 // If we cared, we might do:
900 // (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 => (MOVLconst [0])
901
902 // Convert constant subtracts to constant adds
903 (SUBLconst [c] x) => (ADDLconst [-c] x)
904
905 // generic constant folding
906 // TODO: more of this
907 (ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d])
908 (ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x)
909 (SARLconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)])
910 (SARWconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)])
911 (SARBconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)])
912 (NEGL (MOVLconst [c])) => (MOVLconst [-c])
913 (MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d])
914 (ANDLconst [c] (MOVLconst [d])) => (MOVLconst [c&d])
915 (ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d])
916 (XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d])
917 (NOTL (MOVLconst [c])) => (MOVLconst [^c])
918
919 // generic simplifications
920 // TODO: more of this
921 (ADDL x (NEGL y)) => (SUBL x y)
922 (SUBL x x) => (MOVLconst [0])
923 (ANDL x x) => x
924 (ORL x x) => x
925 (XORL x x) => (MOVLconst [0])
926
927 // checking AND against 0.
928 (CMP(L|W|B)const l:(ANDL x y) [0]) && l.Uses==1 => (TEST(L|W|B) x y)
929 (CMPLconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTLconst [c] x)
930 (CMPWconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTWconst [int16(c)] x)
931 (CMPBconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTBconst [int8(c)] x)
932
933 // TEST %reg,%reg is shorter than CMP
934 (CMP(L|W|B)const x [0]) => (TEST(L|W|B) x x)
935
936 // Convert LEAL1 back to ADDL if we can
937 (LEAL1 [0] {nil} x y) => (ADDL x y)
938
939 // Combining byte loads into larger (unaligned) loads.
940 // There are many ways these combinations could occur. This is
941 // designed to match the way encoding/binary.LittleEndian does it.
942 (ORL x0:(MOVBload [i0] {s} p mem)
943 s0:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem)))
944 && i1 == i0+1
945 && x0.Uses == 1
946 && x1.Uses == 1
947 && s0.Uses == 1
948 && mergePoint(b,x0,x1) != nil
949 && clobber(x0, x1, s0)
950 => @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem)
951
952 (ORL x0:(MOVBload [i] {s} p0 mem)
953 s0:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem)))
954 && x0.Uses == 1
955 && x1.Uses == 1
956 && s0.Uses == 1
957 && sequentialAddresses(p0, p1, 1)
958 && mergePoint(b,x0,x1) != nil
959 && clobber(x0, x1, s0)
960 => @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem)
961
962 (ORL o0:(ORL
963 x0:(MOVWload [i0] {s} p mem)
964 s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem)))
965 s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem)))
966 && i2 == i0+2
967 && i3 == i0+3
968 && x0.Uses == 1
969 && x1.Uses == 1
970 && x2.Uses == 1
971 && s0.Uses == 1
972 && s1.Uses == 1
973 && o0.Uses == 1
974 && mergePoint(b,x0,x1,x2) != nil
975 && clobber(x0, x1, x2, s0, s1, o0)
976 => @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem)
977
978 (ORL o0:(ORL
979 x0:(MOVWload [i] {s} p0 mem)
980 s0:(SHLLconst [16] x1:(MOVBload [i] {s} p1 mem)))
981 s1:(SHLLconst [24] x2:(MOVBload [i] {s} p2 mem)))
982 && x0.Uses == 1
983 && x1.Uses == 1
984 && x2.Uses == 1
985 && s0.Uses == 1
986 && s1.Uses == 1
987 && o0.Uses == 1
988 && sequentialAddresses(p0, p1, 2)
989 && sequentialAddresses(p1, p2, 1)
990 && mergePoint(b,x0,x1,x2) != nil
991 && clobber(x0, x1, x2, s0, s1, o0)
992 => @mergePoint(b,x0,x1,x2) (MOVLload [i] {s} p0 mem)
993
994 // Combine constant stores into larger (unaligned) stores.
995 (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem))
996 && x.Uses == 1
997 && a.Off() + 1 == c.Off()
998 && clobber(x)
999 => (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p mem)
1000 (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem))
1001 && x.Uses == 1
1002 && a.Off() + 1 == c.Off()
1003 && clobber(x)
1004 => (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p mem)
1005
1006 (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem))
1007 && x.Uses == 1
1008 && a.Off() == c.Off()
1009 && sequentialAddresses(p0, p1, 1)
1010 && clobber(x)
1011 => (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem)
1012 (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem))
1013 && x.Uses == 1
1014 && a.Off() == c.Off()
1015 && sequentialAddresses(p0, p1, 1)
1016 && clobber(x)
1017 => (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem)
1018
1019 (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem))
1020 && x.Uses == 1
1021 && a.Off() + 2 == c.Off()
1022 && clobber(x)
1023 => (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p mem)
1024 (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem))
1025 && x.Uses == 1
1026 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off()
1027 && clobber(x)
1028 => (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p mem)
1029
1030 (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem))
1031 && x.Uses == 1
1032 && a.Off() == c.Off()
1033 && sequentialAddresses(p0, p1, 2)
1034 && clobber(x)
1035 => (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem)
1036 (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem))
1037 && x.Uses == 1
1038 && a.Off() == c.Off()
1039 && sequentialAddresses(p0, p1, 2)
1040 && clobber(x)
1041 => (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem)
1042
1043 // Combine stores into larger (unaligned) stores.
1044 (MOVBstore [i] {s} p (SHR(W|L)const [8] w) x:(MOVBstore [i-1] {s} p w mem))
1045 && x.Uses == 1
1046 && clobber(x)
1047 => (MOVWstore [i-1] {s} p w mem)
1048 (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHR(W|L)const [8] w) mem))
1049 && x.Uses == 1
1050 && clobber(x)
1051 => (MOVWstore [i] {s} p w mem)
1052 (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem))
1053 && x.Uses == 1
1054 && clobber(x)
1055 => (MOVWstore [i-1] {s} p w0 mem)
1056
1057 (MOVBstore [i] {s} p1 (SHR(W|L)const [8] w) x:(MOVBstore [i] {s} p0 w mem))
1058 && x.Uses == 1
1059 && sequentialAddresses(p0, p1, 1)
1060 && clobber(x)
1061 => (MOVWstore [i] {s} p0 w mem)
1062 (MOVBstore [i] {s} p0 w x:(MOVBstore {s} [i] p1 (SHR(W|L)const [8] w) mem))
1063 && x.Uses == 1
1064 && sequentialAddresses(p0, p1, 1)
1065 && clobber(x)
1066 => (MOVWstore [i] {s} p0 w mem)
1067 (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem))
1068 && x.Uses == 1
1069 && sequentialAddresses(p0, p1, 1)
1070 && clobber(x)
1071 => (MOVWstore [i] {s} p0 w0 mem)
1072
1073 (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem))
1074 && x.Uses == 1
1075 && clobber(x)
1076 => (MOVLstore [i-2] {s} p w mem)
1077 (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem))
1078 && x.Uses == 1
1079 && clobber(x)
1080 => (MOVLstore [i-2] {s} p w0 mem)
1081
1082 (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem))
1083 && x.Uses == 1
1084 && sequentialAddresses(p0, p1, 2)
1085 && clobber(x)
1086 => (MOVLstore [i] {s} p0 w mem)
1087 (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem))
1088 && x.Uses == 1
1089 && sequentialAddresses(p0, p1, 2)
1090 && clobber(x)
1091 => (MOVLstore [i] {s} p0 w0 mem)
1092
1093 // For PIC, break floating-point constant loading into two instructions so we have
1094 // a register to use for holding the address of the constant pool entry.
1095 (MOVSSconst [c]) && config.ctxt.Flag_shared => (MOVSSconst2 (MOVSSconst1 [c]))
1096 (MOVSDconst [c]) && config.ctxt.Flag_shared => (MOVSDconst2 (MOVSDconst1 [c]))
1097
1098 (CMP(L|W|B) l:(MOV(L|W|B)load {sym} [off] ptr mem) x) && canMergeLoad(v, l) && clobber(l) => (CMP(L|W|B)load {sym} [off] ptr x mem)
1099 (CMP(L|W|B) x l:(MOV(L|W|B)load {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (InvertFlags (CMP(L|W|B)load {sym} [off] ptr x mem))
1100
1101 (CMP(L|W|B)const l:(MOV(L|W|B)load {sym} [off] ptr mem) [c])
1102 && l.Uses == 1
1103 && clobber(l) =>
1104 @l.Block (CMP(L|W|B)constload {sym} [makeValAndOff(int32(c),off)] ptr mem)
1105
1106 (CMPLload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
1107 (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem)
1108 (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem)
1109
1110 (MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read8(sym, int64(off)))])
1111 (MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1112 (MOVLload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1113
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