1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 (Add(Ptr|64|32|16|8) ...) => (ADDV ...)
6 (Add(32|64)F ...) => (ADD(F|D) ...)
7
8 (Sub(Ptr|64|32|16|8) ...) => (SUBV ...)
9 (Sub(32|64)F ...) => (SUB(F|D) ...)
10
11 (Mul(64|32|16|8) x y) => (Select1 (MULVU x y))
12 (Mul(32|64)F ...) => (MUL(F|D) ...)
13 (Mul64uhilo ...) => (MULVU ...)
14 (Select0 (Mul64uover x y)) => (Select1 <typ.UInt64> (MULVU x y))
15 (Select1 (Mul64uover x y)) => (SGTU <typ.Bool> (Select0 <typ.UInt64> (MULVU x y)) (MOVVconst <typ.UInt64> [0]))
16
17 (Hmul64 x y) => (Select0 (MULV x y))
18 (Hmul64u x y) => (Select0 (MULVU x y))
19 (Hmul32 x y) => (SRAVconst (Select1 <typ.Int64> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32])
20 (Hmul32u x y) => (SRLVconst (Select1 <typ.UInt64> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32])
21
22 (Div64 x y) => (Select1 (DIVV x y))
23 (Div64u x y) => (Select1 (DIVVU x y))
24 (Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
25 (Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
26 (Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
27 (Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
28 (Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
29 (Div8u x y) => (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
30 (Div(32|64)F ...) => (DIV(F|D) ...)
31
32 (Mod64 x y) => (Select0 (DIVV x y))
33 (Mod64u x y) => (Select0 (DIVVU x y))
34 (Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
35 (Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
36 (Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
37 (Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
38 (Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
39 (Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
40
41 // (x + y) / 2 with x>=y => (x - y) / 2 + y
42 (Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
43
44 (And(64|32|16|8) ...) => (AND ...)
45 (Or(64|32|16|8) ...) => (OR ...)
46 (Xor(64|32|16|8) ...) => (XOR ...)
47
48 // shifts
49 // hardware instruction uses only the low 6 bits of the shift
50 // we compare to 64 to ensure Go semantics for large shifts
51 (Lsh64x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
52 (Lsh64x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
53 (Lsh64x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
54 (Lsh64x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
55
56 (Lsh32x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
57 (Lsh32x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
58 (Lsh32x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
59 (Lsh32x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
60
61 (Lsh16x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
62 (Lsh16x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
63 (Lsh16x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
64 (Lsh16x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
65
66 (Lsh8x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
67 (Lsh8x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
68 (Lsh8x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
69 (Lsh8x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
70
71 (Rsh64Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> x y))
72 (Rsh64Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y)))
73 (Rsh64Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y)))
74 (Rsh64Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y)))
75
76 (Rsh32Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y))
77 (Rsh32Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y)))
78 (Rsh32Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y)))
79 (Rsh32Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y)))
80
81 (Rsh16Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y))
82 (Rsh16Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y)))
83 (Rsh16Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y)))
84 (Rsh16Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y)))
85
86 (Rsh8Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y))
87 (Rsh8Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y)))
88 (Rsh8Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y)))
89 (Rsh8Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y)))
90
91 (Rsh64x64 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
92 (Rsh64x32 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
93 (Rsh64x16 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
94 (Rsh64x8 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
95
96 (Rsh32x64 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
97 (Rsh32x32 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
98 (Rsh32x16 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
99 (Rsh32x8 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
100
101 (Rsh16x64 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
102 (Rsh16x32 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
103 (Rsh16x16 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
104 (Rsh16x8 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
105
106 (Rsh8x64 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
107 (Rsh8x32 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
108 (Rsh8x16 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
109 (Rsh8x8 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
110
111 // rotates
112 (RotateLeft8 <t> x (MOVVconst [c])) => (Or8 (Lsh8x64 <t> x (MOVVconst [c&7])) (Rsh8Ux64 <t> x (MOVVconst [-c&7])))
113 (RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
114 (RotateLeft32 <t> x (MOVVconst [c])) => (Or32 (Lsh32x64 <t> x (MOVVconst [c&31])) (Rsh32Ux64 <t> x (MOVVconst [-c&31])))
115 (RotateLeft64 <t> x (MOVVconst [c])) => (Or64 (Lsh64x64 <t> x (MOVVconst [c&63])) (Rsh64Ux64 <t> x (MOVVconst [-c&63])))
116
117 // unary ops
118 (Neg(64|32|16|8) ...) => (NEGV ...)
119 (Neg(32|64)F ...) => (NEG(F|D) ...)
120
121 (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
122
123 (Sqrt ...) => (SQRTD ...)
124 (Sqrt32 ...) => (SQRTF ...)
125
126 // boolean ops -- booleans are represented with 0=false, 1=true
127 (AndB ...) => (AND ...)
128 (OrB ...) => (OR ...)
129 (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
130 (NeqB ...) => (XOR ...)
131 (Not x) => (XORconst [1] x)
132
133 // constants
134 (Const(64|32|16|8) [val]) => (MOVVconst [int64(val)])
135 (Const(32|64)F [val]) => (MOV(F|D)const [float64(val)])
136 (ConstNil) => (MOVVconst [0])
137 (ConstBool [t]) => (MOVVconst [int64(b2i(t))])
138
139 (Slicemask <t> x) => (SRAVconst (NEGV <t> x) [63])
140
141 // truncations
142 // Because we ignore high parts of registers, truncates are just copies.
143 (Trunc16to8 ...) => (Copy ...)
144 (Trunc32to8 ...) => (Copy ...)
145 (Trunc32to16 ...) => (Copy ...)
146 (Trunc64to8 ...) => (Copy ...)
147 (Trunc64to16 ...) => (Copy ...)
148 (Trunc64to32 ...) => (Copy ...)
149
150 // Zero-/Sign-extensions
151 (ZeroExt8to16 ...) => (MOVBUreg ...)
152 (ZeroExt8to32 ...) => (MOVBUreg ...)
153 (ZeroExt16to32 ...) => (MOVHUreg ...)
154 (ZeroExt8to64 ...) => (MOVBUreg ...)
155 (ZeroExt16to64 ...) => (MOVHUreg ...)
156 (ZeroExt32to64 ...) => (MOVWUreg ...)
157
158 (SignExt8to16 ...) => (MOVBreg ...)
159 (SignExt8to32 ...) => (MOVBreg ...)
160 (SignExt16to32 ...) => (MOVHreg ...)
161 (SignExt8to64 ...) => (MOVBreg ...)
162 (SignExt16to64 ...) => (MOVHreg ...)
163 (SignExt32to64 ...) => (MOVWreg ...)
164
165 // float <=> int conversion
166 (Cvt32to32F ...) => (MOVWF ...)
167 (Cvt32to64F ...) => (MOVWD ...)
168 (Cvt64to32F ...) => (MOVVF ...)
169 (Cvt64to64F ...) => (MOVVD ...)
170 (Cvt32Fto32 ...) => (TRUNCFW ...)
171 (Cvt64Fto32 ...) => (TRUNCDW ...)
172 (Cvt32Fto64 ...) => (TRUNCFV ...)
173 (Cvt64Fto64 ...) => (TRUNCDV ...)
174 (Cvt32Fto64F ...) => (MOVFD ...)
175 (Cvt64Fto32F ...) => (MOVDF ...)
176
177 (CvtBoolToUint8 ...) => (Copy ...)
178
179 (Round(32|64)F ...) => (Copy ...)
180
181 // comparisons
182 (Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)))
183 (Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y)))
184 (Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)))
185 (Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y))
186 (EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y))
187 (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
188
189 (Neq8 x y) => (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0]))
190 (Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0]))
191 (Neq32 x y) => (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0]))
192 (Neq64 x y) => (SGTU (XOR x y) (MOVVconst [0]))
193 (NeqPtr x y) => (SGTU (XOR x y) (MOVVconst [0]))
194 (Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
195
196 (Less8 x y) => (SGT (SignExt8to64 y) (SignExt8to64 x))
197 (Less16 x y) => (SGT (SignExt16to64 y) (SignExt16to64 x))
198 (Less32 x y) => (SGT (SignExt32to64 y) (SignExt32to64 x))
199 (Less64 x y) => (SGT y x)
200 (Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN
201
202 (Less8U x y) => (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))
203 (Less16U x y) => (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))
204 (Less32U x y) => (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))
205 (Less64U x y) => (SGTU y x)
206
207 (Leq8 x y) => (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y)))
208 (Leq16 x y) => (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y)))
209 (Leq32 x y) => (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y)))
210 (Leq64 x y) => (XOR (MOVVconst [1]) (SGT x y))
211 (Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN
212
213 (Leq8U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)))
214 (Leq16U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)))
215 (Leq32U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)))
216 (Leq64U x y) => (XOR (MOVVconst [1]) (SGTU x y))
217
218 (OffPtr [off] ptr:(SP)) && is32Bit(off) => (MOVVaddr [int32(off)] ptr)
219 (OffPtr [off] ptr) => (ADDVconst [off] ptr)
220
221 (Addr {sym} base) => (MOVVaddr {sym} base)
222 (LocalAddr {sym} base _) => (MOVVaddr {sym} base)
223
224 // loads
225 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
226 (Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
227 (Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
228 (Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
229 (Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
230 (Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
231 (Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
232 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
233 (Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
234 (Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
235
236 // stores
237 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
238 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
239 (Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
240 (Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVVstore ptr val mem)
241 (Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem)
242 (Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem)
243
244 // zeroing
245 (Zero [0] _ mem) => mem
246 (Zero [1] ptr mem) => (MOVBstore ptr (MOVVconst [0]) mem)
247 (Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 =>
248 (MOVHstore ptr (MOVVconst [0]) mem)
249 (Zero [2] ptr mem) =>
250 (MOVBstore [1] ptr (MOVVconst [0])
251 (MOVBstore [0] ptr (MOVVconst [0]) mem))
252 (Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 =>
253 (MOVWstore ptr (MOVVconst [0]) mem)
254 (Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 =>
255 (MOVHstore [2] ptr (MOVVconst [0])
256 (MOVHstore [0] ptr (MOVVconst [0]) mem))
257 (Zero [4] ptr mem) =>
258 (MOVBstore [3] ptr (MOVVconst [0])
259 (MOVBstore [2] ptr (MOVVconst [0])
260 (MOVBstore [1] ptr (MOVVconst [0])
261 (MOVBstore [0] ptr (MOVVconst [0]) mem))))
262 (Zero [8] {t} ptr mem) && t.Alignment()%8 == 0 =>
263 (MOVVstore ptr (MOVVconst [0]) mem)
264 (Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
265 (MOVWstore [4] ptr (MOVVconst [0])
266 (MOVWstore [0] ptr (MOVVconst [0]) mem))
267 (Zero [8] {t} ptr mem) && t.Alignment()%2 == 0 =>
268 (MOVHstore [6] ptr (MOVVconst [0])
269 (MOVHstore [4] ptr (MOVVconst [0])
270 (MOVHstore [2] ptr (MOVVconst [0])
271 (MOVHstore [0] ptr (MOVVconst [0]) mem))))
272
273 (Zero [3] ptr mem) =>
274 (MOVBstore [2] ptr (MOVVconst [0])
275 (MOVBstore [1] ptr (MOVVconst [0])
276 (MOVBstore [0] ptr (MOVVconst [0]) mem)))
277 (Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 =>
278 (MOVHstore [4] ptr (MOVVconst [0])
279 (MOVHstore [2] ptr (MOVVconst [0])
280 (MOVHstore [0] ptr (MOVVconst [0]) mem)))
281 (Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 =>
282 (MOVWstore [8] ptr (MOVVconst [0])
283 (MOVWstore [4] ptr (MOVVconst [0])
284 (MOVWstore [0] ptr (MOVVconst [0]) mem)))
285 (Zero [16] {t} ptr mem) && t.Alignment()%8 == 0 =>
286 (MOVVstore [8] ptr (MOVVconst [0])
287 (MOVVstore [0] ptr (MOVVconst [0]) mem))
288 (Zero [24] {t} ptr mem) && t.Alignment()%8 == 0 =>
289 (MOVVstore [16] ptr (MOVVconst [0])
290 (MOVVstore [8] ptr (MOVVconst [0])
291 (MOVVstore [0] ptr (MOVVconst [0]) mem)))
292
293 // medium zeroing uses a duff device
294 // 8, and 128 are magic constants, see runtime/mkduff.go
295 (Zero [s] {t} ptr mem)
296 && s%8 == 0 && s > 24 && s <= 8*128
297 && t.Alignment()%8 == 0 && !config.noDuffDevice =>
298 (DUFFZERO [8 * (128 - s/8)] ptr mem)
299
300 // large or unaligned zeroing uses a loop
301 (Zero [s] {t} ptr mem)
302 && (s > 8*128 || config.noDuffDevice) || t.Alignment()%8 != 0 =>
303 (LoweredZero [t.Alignment()]
304 ptr
305 (ADDVconst <ptr.Type> ptr [s-moveSize(t.Alignment(), config)])
306 mem)
307
308 // moves
309 (Move [0] _ _ mem) => mem
310 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
311 (Move [2] {t} dst src mem) && t.Alignment()%2 == 0 =>
312 (MOVHstore dst (MOVHload src mem) mem)
313 (Move [2] dst src mem) =>
314 (MOVBstore [1] dst (MOVBload [1] src mem)
315 (MOVBstore dst (MOVBload src mem) mem))
316 (Move [4] {t} dst src mem) && t.Alignment()%4 == 0 =>
317 (MOVWstore dst (MOVWload src mem) mem)
318 (Move [4] {t} dst src mem) && t.Alignment()%2 == 0 =>
319 (MOVHstore [2] dst (MOVHload [2] src mem)
320 (MOVHstore dst (MOVHload src mem) mem))
321 (Move [4] dst src mem) =>
322 (MOVBstore [3] dst (MOVBload [3] src mem)
323 (MOVBstore [2] dst (MOVBload [2] src mem)
324 (MOVBstore [1] dst (MOVBload [1] src mem)
325 (MOVBstore dst (MOVBload src mem) mem))))
326 (Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
327 (MOVVstore dst (MOVVload src mem) mem)
328 (Move [8] {t} dst src mem) && t.Alignment()%4 == 0 =>
329 (MOVWstore [4] dst (MOVWload [4] src mem)
330 (MOVWstore dst (MOVWload src mem) mem))
331 (Move [8] {t} dst src mem) && t.Alignment()%2 == 0 =>
332 (MOVHstore [6] dst (MOVHload [6] src mem)
333 (MOVHstore [4] dst (MOVHload [4] src mem)
334 (MOVHstore [2] dst (MOVHload [2] src mem)
335 (MOVHstore dst (MOVHload src mem) mem))))
336
337 (Move [3] dst src mem) =>
338 (MOVBstore [2] dst (MOVBload [2] src mem)
339 (MOVBstore [1] dst (MOVBload [1] src mem)
340 (MOVBstore dst (MOVBload src mem) mem)))
341 (Move [6] {t} dst src mem) && t.Alignment()%2 == 0 =>
342 (MOVHstore [4] dst (MOVHload [4] src mem)
343 (MOVHstore [2] dst (MOVHload [2] src mem)
344 (MOVHstore dst (MOVHload src mem) mem)))
345 (Move [12] {t} dst src mem) && t.Alignment()%4 == 0 =>
346 (MOVWstore [8] dst (MOVWload [8] src mem)
347 (MOVWstore [4] dst (MOVWload [4] src mem)
348 (MOVWstore dst (MOVWload src mem) mem)))
349 (Move [16] {t} dst src mem) && t.Alignment()%8 == 0 =>
350 (MOVVstore [8] dst (MOVVload [8] src mem)
351 (MOVVstore dst (MOVVload src mem) mem))
352 (Move [24] {t} dst src mem) && t.Alignment()%8 == 0 =>
353 (MOVVstore [16] dst (MOVVload [16] src mem)
354 (MOVVstore [8] dst (MOVVload [8] src mem)
355 (MOVVstore dst (MOVVload src mem) mem)))
356
357 // medium move uses a duff device
358 (Move [s] {t} dst src mem)
359 && s%8 == 0 && s >= 24 && s <= 8*128 && t.Alignment()%8 == 0
360 && !config.noDuffDevice && logLargeCopy(v, s) =>
361 (DUFFCOPY [16 * (128 - s/8)] dst src mem)
362 // 16 and 128 are magic constants. 16 is the number of bytes to encode:
363 // MOVV (R1), R23
364 // ADDV $8, R1
365 // MOVV R23, (R2)
366 // ADDV $8, R2
367 // and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.
368
369 // large or unaligned move uses a loop
370 (Move [s] {t} dst src mem)
371 && s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0 =>
372 (LoweredMove [t.Alignment()]
373 dst
374 src
375 (ADDVconst <src.Type> src [s-moveSize(t.Alignment(), config)])
376 mem)
377
378 // calls
379 (StaticCall ...) => (CALLstatic ...)
380 (ClosureCall ...) => (CALLclosure ...)
381 (InterCall ...) => (CALLinter ...)
382 (TailCall ...) => (CALLtail ...)
383
384 // atomic intrinsics
385 (AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...)
386 (AtomicLoadPtr ...) => (LoweredAtomicLoad64 ...)
387
388 (AtomicStore(8|32|64) ...) => (LoweredAtomicStore(8|32|64) ...)
389 (AtomicStorePtrNoWB ...) => (LoweredAtomicStore64 ...)
390
391 (AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...)
392
393 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
394
395 (AtomicCompareAndSwap(32|64) ...) => (LoweredAtomicCas(32|64) ...)
396
397 // checks
398 (NilCheck ...) => (LoweredNilCheck ...)
399 (IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
400 (IsInBounds idx len) => (SGTU len idx)
401 (IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len))
402
403 // pseudo-ops
404 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
405 (GetCallerSP ...) => (LoweredGetCallerSP ...)
406 (GetCallerPC ...) => (LoweredGetCallerPC ...)
407
408 (If cond yes no) => (NE cond yes no)
409
410 // Write barrier.
411 (WB ...) => (LoweredWB ...)
412
413 (PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
414 (PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
415 (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
416
417 // Optimizations
418
419 // Absorb boolean tests into block
420 (NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
421 (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
422 (EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
423 (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
424 (NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
425 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no)
426 (NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no)
427 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no)
428 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no)
429 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no)
430 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no)
431 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no)
432 (NE (SGTUconst [1] x) yes no) => (EQ x yes no)
433 (EQ (SGTUconst [1] x) yes no) => (NE x yes no)
434 (NE (SGTU x (MOVVconst [0])) yes no) => (NE x yes no)
435 (EQ (SGTU x (MOVVconst [0])) yes no) => (EQ x yes no)
436 (NE (SGTconst [0] x) yes no) => (LTZ x yes no)
437 (EQ (SGTconst [0] x) yes no) => (GEZ x yes no)
438 (NE (SGT x (MOVVconst [0])) yes no) => (GTZ x yes no)
439 (EQ (SGT x (MOVVconst [0])) yes no) => (LEZ x yes no)
440
441 // fold offset into address
442 (ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) => (MOVVaddr [int32(off1)+int32(off2)] {sym} ptr)
443
444 // fold address into load/store
445 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBload [off1+int32(off2)] {sym} ptr mem)
446 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBUload [off1+int32(off2)] {sym} ptr mem)
447 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHload [off1+int32(off2)] {sym} ptr mem)
448 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHUload [off1+int32(off2)] {sym} ptr mem)
449 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWload [off1+int32(off2)] {sym} ptr mem)
450 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWUload [off1+int32(off2)] {sym} ptr mem)
451 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVVload [off1+int32(off2)] {sym} ptr mem)
452 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVFload [off1+int32(off2)] {sym} ptr mem)
453 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVDload [off1+int32(off2)] {sym} ptr mem)
454
455 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
456 (MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
457 (MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
458 (MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVVstore [off1+int32(off2)] {sym} ptr val mem)
459 (MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVFstore [off1+int32(off2)] {sym} ptr val mem)
460 (MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
461 (MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBstorezero [off1+int32(off2)] {sym} ptr mem)
462 (MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHstorezero [off1+int32(off2)] {sym} ptr mem)
463 (MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWstorezero [off1+int32(off2)] {sym} ptr mem)
464 (MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVVstorezero [off1+int32(off2)] {sym} ptr mem)
465
466 (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
467 (MOVBload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
468 (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
469 (MOVBUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
470 (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
471 (MOVHload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
472 (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
473 (MOVHUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
474 (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
475 (MOVWload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
476 (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
477 (MOVWUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
478 (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
479 (MOVVload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
480 (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
481 (MOVFload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
482 (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
483 (MOVDload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
484
485 (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
486 (MOVBstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
487 (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
488 (MOVHstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
489 (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
490 (MOVWstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
491 (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
492 (MOVVstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
493 (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
494 (MOVFstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
495 (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
496 (MOVDstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
497 (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
498 (MOVBstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
499 (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
500 (MOVHstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
501 (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
502 (MOVWstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
503 (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
504 (MOVVstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
505
506 // store zero
507 (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
508 (MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
509 (MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
510 (MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) => (MOVVstorezero [off] {sym} ptr mem)
511
512 // don't extend after proper load
513 (MOVBreg x:(MOVBload _ _)) => (MOVVreg x)
514 (MOVBUreg x:(MOVBUload _ _)) => (MOVVreg x)
515 (MOVHreg x:(MOVBload _ _)) => (MOVVreg x)
516 (MOVHreg x:(MOVBUload _ _)) => (MOVVreg x)
517 (MOVHreg x:(MOVHload _ _)) => (MOVVreg x)
518 (MOVHUreg x:(MOVBUload _ _)) => (MOVVreg x)
519 (MOVHUreg x:(MOVHUload _ _)) => (MOVVreg x)
520 (MOVWreg x:(MOVBload _ _)) => (MOVVreg x)
521 (MOVWreg x:(MOVBUload _ _)) => (MOVVreg x)
522 (MOVWreg x:(MOVHload _ _)) => (MOVVreg x)
523 (MOVWreg x:(MOVHUload _ _)) => (MOVVreg x)
524 (MOVWreg x:(MOVWload _ _)) => (MOVVreg x)
525 (MOVWUreg x:(MOVBUload _ _)) => (MOVVreg x)
526 (MOVWUreg x:(MOVHUload _ _)) => (MOVVreg x)
527 (MOVWUreg x:(MOVWUload _ _)) => (MOVVreg x)
528
529 // fold double extensions
530 (MOVBreg x:(MOVBreg _)) => (MOVVreg x)
531 (MOVBUreg x:(MOVBUreg _)) => (MOVVreg x)
532 (MOVHreg x:(MOVBreg _)) => (MOVVreg x)
533 (MOVHreg x:(MOVBUreg _)) => (MOVVreg x)
534 (MOVHreg x:(MOVHreg _)) => (MOVVreg x)
535 (MOVHUreg x:(MOVBUreg _)) => (MOVVreg x)
536 (MOVHUreg x:(MOVHUreg _)) => (MOVVreg x)
537 (MOVWreg x:(MOVBreg _)) => (MOVVreg x)
538 (MOVWreg x:(MOVBUreg _)) => (MOVVreg x)
539 (MOVWreg x:(MOVHreg _)) => (MOVVreg x)
540 (MOVWreg x:(MOVWreg _)) => (MOVVreg x)
541 (MOVWUreg x:(MOVBUreg _)) => (MOVVreg x)
542 (MOVWUreg x:(MOVHUreg _)) => (MOVVreg x)
543 (MOVWUreg x:(MOVWUreg _)) => (MOVVreg x)
544
545 // don't extend before store
546 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
547 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
548 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
549 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
550 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
551 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
552 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
553 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
554 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
555 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
556 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
557 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
558
559 // if a register move has only 1 use, just use the same register without emitting instruction
560 // MOVVnop doesn't emit instruction, only for ensuring the type.
561 (MOVVreg x) && x.Uses == 1 => (MOVVnop x)
562
563 // TODO: we should be able to get rid of MOVVnop all together.
564 // But for now, this is enough to get rid of lots of them.
565 (MOVVnop (MOVVconst [c])) => (MOVVconst [c])
566
567 // fold constant into arithmatic ops
568 (ADDV x (MOVVconst [c])) && is32Bit(c) => (ADDVconst [c] x)
569 (SUBV x (MOVVconst [c])) && is32Bit(c) => (SUBVconst [c] x)
570 (AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x)
571 (OR x (MOVVconst [c])) && is32Bit(c) => (ORconst [c] x)
572 (XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x)
573 (NOR x (MOVVconst [c])) && is32Bit(c) => (NORconst [c] x)
574
575 (SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
576 (SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
577 (SRAV x (MOVVconst [c])) && uint64(c)>=64 => (SRAVconst x [63])
578 (SLLV x (MOVVconst [c])) => (SLLVconst x [c])
579 (SRLV x (MOVVconst [c])) => (SRLVconst x [c])
580 (SRAV x (MOVVconst [c])) => (SRAVconst x [c])
581
582 (SGT (MOVVconst [c]) x) && is32Bit(c) => (SGTconst [c] x)
583 (SGTU (MOVVconst [c]) x) && is32Bit(c) => (SGTUconst [c] x)
584
585 // mul by constant
586 (Select1 (MULVU x (MOVVconst [-1]))) => (NEGV x)
587 (Select1 (MULVU _ (MOVVconst [0]))) => (MOVVconst [0])
588 (Select1 (MULVU x (MOVVconst [1]))) => x
589 (Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SLLVconst [log64(c)] x)
590
591 // div by constant
592 (Select1 (DIVVU x (MOVVconst [1]))) => x
593 (Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SRLVconst [log64(c)] x)
594 (Select0 (DIVVU _ (MOVVconst [1]))) => (MOVVconst [0]) // mod
595 (Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (ANDconst [c-1] x) // mod
596
597 // generic simplifications
598 (ADDV x (NEGV y)) => (SUBV x y)
599 (SUBV x x) => (MOVVconst [0])
600 (SUBV (MOVVconst [0]) x) => (NEGV x)
601 (AND x x) => x
602 (OR x x) => x
603 (XOR x x) => (MOVVconst [0])
604
605 // remove redundant *const ops
606 (ADDVconst [0] x) => x
607 (SUBVconst [0] x) => x
608 (ANDconst [0] _) => (MOVVconst [0])
609 (ANDconst [-1] x) => x
610 (ORconst [0] x) => x
611 (ORconst [-1] _) => (MOVVconst [-1])
612 (XORconst [0] x) => x
613 (XORconst [-1] x) => (NORconst [0] x)
614
615 // generic constant folding
616 (ADDVconst [c] (MOVVconst [d])) => (MOVVconst [c+d])
617 (ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) => (ADDVconst [c+d] x)
618 (ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) => (ADDVconst [c-d] x)
619 (SUBVconst [c] (MOVVconst [d])) => (MOVVconst [d-c])
620 (SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) => (ADDVconst [-c-d] x)
621 (SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) => (ADDVconst [-c+d] x)
622 (SLLVconst [c] (MOVVconst [d])) => (MOVVconst [d<<uint64(c)])
623 (SRLVconst [c] (MOVVconst [d])) => (MOVVconst [int64(uint64(d)>>uint64(c))])
624 (SRAVconst [c] (MOVVconst [d])) => (MOVVconst [d>>uint64(c)])
625 (Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [c*d])
626 (Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c/d])
627 (Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)/uint64(d))])
628 (Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c%d]) // mod
629 (Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod
630 (ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d])
631 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
632 (ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d])
633 (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x)
634 (XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d])
635 (XORconst [c] (XORconst [d] x)) && is32Bit(c^d) => (XORconst [c^d] x)
636 (NORconst [c] (MOVVconst [d])) => (MOVVconst [^(c|d)])
637 (NEGV (MOVVconst [c])) => (MOVVconst [-c])
638 (MOVBreg (MOVVconst [c])) => (MOVVconst [int64(int8(c))])
639 (MOVBUreg (MOVVconst [c])) => (MOVVconst [int64(uint8(c))])
640 (MOVHreg (MOVVconst [c])) => (MOVVconst [int64(int16(c))])
641 (MOVHUreg (MOVVconst [c])) => (MOVVconst [int64(uint16(c))])
642 (MOVWreg (MOVVconst [c])) => (MOVVconst [int64(int32(c))])
643 (MOVWUreg (MOVVconst [c])) => (MOVVconst [int64(uint32(c))])
644 (MOVVreg (MOVVconst [c])) => (MOVVconst [c])
645 (LoweredAtomicStore(32|64) ptr (MOVVconst [0]) mem) => (LoweredAtomicStorezero(32|64) ptr mem)
646 (LoweredAtomicAdd32 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst32 [int32(c)] ptr mem)
647 (LoweredAtomicAdd64 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst64 [c] ptr mem)
648
649 // constant comparisons
650 (SGTconst [c] (MOVVconst [d])) && c>d => (MOVVconst [1])
651 (SGTconst [c] (MOVVconst [d])) && c<=d => (MOVVconst [0])
652 (SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) => (MOVVconst [1])
653 (SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) => (MOVVconst [0])
654
655 // other known comparisons
656 (SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVVconst [1])
657 (SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVVconst [0])
658 (SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVVconst [1])
659 (SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVVconst [0])
660 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) => (MOVVconst [1])
661 (SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVVconst [1])
662 (SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVVconst [0])
663 (SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVVconst [1])
664 (SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVVconst [0])
665 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) => (MOVVconst [1])
666 (SGTconst [c] (MOVWUreg _)) && c < 0 => (MOVVconst [0])
667 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVVconst [1])
668 (SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) => (MOVVconst [1])
669 (SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
670 (SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
671
672 // absorb constants into branches
673 (EQ (MOVVconst [0]) yes no) => (First yes no)
674 (EQ (MOVVconst [c]) yes no) && c != 0 => (First no yes)
675 (NE (MOVVconst [0]) yes no) => (First no yes)
676 (NE (MOVVconst [c]) yes no) && c != 0 => (First yes no)
677 (LTZ (MOVVconst [c]) yes no) && c < 0 => (First yes no)
678 (LTZ (MOVVconst [c]) yes no) && c >= 0 => (First no yes)
679 (LEZ (MOVVconst [c]) yes no) && c <= 0 => (First yes no)
680 (LEZ (MOVVconst [c]) yes no) && c > 0 => (First no yes)
681 (GTZ (MOVVconst [c]) yes no) && c > 0 => (First yes no)
682 (GTZ (MOVVconst [c]) yes no) && c <= 0 => (First no yes)
683 (GEZ (MOVVconst [c]) yes no) && c >= 0 => (First yes no)
684 (GEZ (MOVVconst [c]) yes no) && c < 0 => (First no yes)
685
686 // fold readonly sym load
687 (MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read8(sym, int64(off)))])
688 (MOVHload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
689 (MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
690 (MOVVload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))])
691
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