a.out.go

     1  // cmd/9c/9.out.h from Vita Nuova.
     2  //
     3  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     6  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7  //	Portions Copyright © 2004,2006 Bruce Ellis
     8  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10  //	Portions Copyright © 2009 The Go Authors. All rights reserved.
    11  //
    12  // Permission is hereby granted, free of charge, to any person obtaining a copy
    13  // of this software and associated documentation files (the "Software"), to deal
    14  // in the Software without restriction, including without limitation the rights
    15  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16  // copies of the Software, and to permit persons to whom the Software is
    17  // furnished to do so, subject to the following conditions:
    18  //
    19  // The above copyright notice and this permission notice shall be included in
    20  // all copies or substantial portions of the Software.
    21  //
    22  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28  // THE SOFTWARE.
    29  
    30  package ppc64
    31  
    32  import "cmd/internal/obj"
    33  
    34  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64
    35  
    36  /*
    37   * powerpc 64
    38   */
    39  const (
    40  	NSNAME = 8
    41  	NSYM   = 50
    42  	NREG   = 32 /* number of general registers */
    43  	NFREG  = 32 /* number of floating point registers */
    44  )
    45  
    46  const (
    47  	/* RBasePPC64 = 4096 */
    48  	/* R0=4096 ... R31=4127 */
    49  	REG_R0 = obj.RBasePPC64 + iota
    50  	REG_R1
    51  	REG_R2
    52  	REG_R3
    53  	REG_R4
    54  	REG_R5
    55  	REG_R6
    56  	REG_R7
    57  	REG_R8
    58  	REG_R9
    59  	REG_R10
    60  	REG_R11
    61  	REG_R12
    62  	REG_R13
    63  	REG_R14
    64  	REG_R15
    65  	REG_R16
    66  	REG_R17
    67  	REG_R18
    68  	REG_R19
    69  	REG_R20
    70  	REG_R21
    71  	REG_R22
    72  	REG_R23
    73  	REG_R24
    74  	REG_R25
    75  	REG_R26
    76  	REG_R27
    77  	REG_R28
    78  	REG_R29
    79  	REG_R30
    80  	REG_R31
    81  
    82  	// CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32
    83  	REG_CR0LT
    84  	REG_CR0GT
    85  	REG_CR0EQ
    86  	REG_CR0SO
    87  	REG_CR1LT
    88  	REG_CR1GT
    89  	REG_CR1EQ
    90  	REG_CR1SO
    91  	REG_CR2LT
    92  	REG_CR2GT
    93  	REG_CR2EQ
    94  	REG_CR2SO
    95  	REG_CR3LT
    96  	REG_CR3GT
    97  	REG_CR3EQ
    98  	REG_CR3SO
    99  	REG_CR4LT
   100  	REG_CR4GT
   101  	REG_CR4EQ
   102  	REG_CR4SO
   103  	REG_CR5LT
   104  	REG_CR5GT
   105  	REG_CR5EQ
   106  	REG_CR5SO
   107  	REG_CR6LT
   108  	REG_CR6GT
   109  	REG_CR6EQ
   110  	REG_CR6SO
   111  	REG_CR7LT
   112  	REG_CR7GT
   113  	REG_CR7EQ
   114  	REG_CR7SO
   115  
   116  	/* Align FPR and VSR vectors such that when masked with 0x3F they produce
   117  	   an equivalent VSX register. */
   118  	/* F0=4160 ... F31=4191 */
   119  	REG_F0
   120  	REG_F1
   121  	REG_F2
   122  	REG_F3
   123  	REG_F4
   124  	REG_F5
   125  	REG_F6
   126  	REG_F7
   127  	REG_F8
   128  	REG_F9
   129  	REG_F10
   130  	REG_F11
   131  	REG_F12
   132  	REG_F13
   133  	REG_F14
   134  	REG_F15
   135  	REG_F16
   136  	REG_F17
   137  	REG_F18
   138  	REG_F19
   139  	REG_F20
   140  	REG_F21
   141  	REG_F22
   142  	REG_F23
   143  	REG_F24
   144  	REG_F25
   145  	REG_F26
   146  	REG_F27
   147  	REG_F28
   148  	REG_F29
   149  	REG_F30
   150  	REG_F31
   151  
   152  	/* V0=4192 ... V31=4223 */
   153  	REG_V0
   154  	REG_V1
   155  	REG_V2
   156  	REG_V3
   157  	REG_V4
   158  	REG_V5
   159  	REG_V6
   160  	REG_V7
   161  	REG_V8
   162  	REG_V9
   163  	REG_V10
   164  	REG_V11
   165  	REG_V12
   166  	REG_V13
   167  	REG_V14
   168  	REG_V15
   169  	REG_V16
   170  	REG_V17
   171  	REG_V18
   172  	REG_V19
   173  	REG_V20
   174  	REG_V21
   175  	REG_V22
   176  	REG_V23
   177  	REG_V24
   178  	REG_V25
   179  	REG_V26
   180  	REG_V27
   181  	REG_V28
   182  	REG_V29
   183  	REG_V30
   184  	REG_V31
   185  
   186  	/* VS0=4224 ... VS63=4287 */
   187  	REG_VS0
   188  	REG_VS1
   189  	REG_VS2
   190  	REG_VS3
   191  	REG_VS4
   192  	REG_VS5
   193  	REG_VS6
   194  	REG_VS7
   195  	REG_VS8
   196  	REG_VS9
   197  	REG_VS10
   198  	REG_VS11
   199  	REG_VS12
   200  	REG_VS13
   201  	REG_VS14
   202  	REG_VS15
   203  	REG_VS16
   204  	REG_VS17
   205  	REG_VS18
   206  	REG_VS19
   207  	REG_VS20
   208  	REG_VS21
   209  	REG_VS22
   210  	REG_VS23
   211  	REG_VS24
   212  	REG_VS25
   213  	REG_VS26
   214  	REG_VS27
   215  	REG_VS28
   216  	REG_VS29
   217  	REG_VS30
   218  	REG_VS31
   219  	REG_VS32
   220  	REG_VS33
   221  	REG_VS34
   222  	REG_VS35
   223  	REG_VS36
   224  	REG_VS37
   225  	REG_VS38
   226  	REG_VS39
   227  	REG_VS40
   228  	REG_VS41
   229  	REG_VS42
   230  	REG_VS43
   231  	REG_VS44
   232  	REG_VS45
   233  	REG_VS46
   234  	REG_VS47
   235  	REG_VS48
   236  	REG_VS49
   237  	REG_VS50
   238  	REG_VS51
   239  	REG_VS52
   240  	REG_VS53
   241  	REG_VS54
   242  	REG_VS55
   243  	REG_VS56
   244  	REG_VS57
   245  	REG_VS58
   246  	REG_VS59
   247  	REG_VS60
   248  	REG_VS61
   249  	REG_VS62
   250  	REG_VS63
   251  
   252  	REG_CR0
   253  	REG_CR1
   254  	REG_CR2
   255  	REG_CR3
   256  	REG_CR4
   257  	REG_CR5
   258  	REG_CR6
   259  	REG_CR7
   260  
   261  	REG_MSR
   262  	REG_FPSCR
   263  	REG_CR
   264  
   265  	REG_SPECIAL = REG_CR0
   266  
   267  	REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
   268  
   269  	REG_XER = REG_SPR0 + 1
   270  	REG_LR  = REG_SPR0 + 8
   271  	REG_CTR = REG_SPR0 + 9
   272  
   273  	REGZERO = REG_R0 /* set to zero */
   274  	REGSP   = REG_R1
   275  	REGSB   = REG_R2
   276  	REGRET  = REG_R3
   277  	REGARG  = -1      /* -1 disables passing the first argument in register */
   278  	REGRT1  = REG_R20 /* reserved for runtime, duffzero and duffcopy */
   279  	REGRT2  = REG_R21 /* reserved for runtime, duffcopy */
   280  	REGMIN  = REG_R7  /* register variables allocated from here to REGMAX */
   281  	REGCTXT = REG_R11 /* context for closures */
   282  	REGTLS  = REG_R13 /* C ABI TLS base pointer */
   283  	REGMAX  = REG_R27
   284  	REGEXT  = REG_R30 /* external registers allocated from here down */
   285  	REGG    = REG_R30 /* G */
   286  	REGTMP  = REG_R31 /* used by the linker */
   287  	FREGRET = REG_F0
   288  	FREGMIN = REG_F17 /* first register variable */
   289  	FREGMAX = REG_F26 /* last register variable for 9g only */
   290  	FREGEXT = REG_F26 /* first external register */
   291  )
   292  
   293  // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI
   294  // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
   295  var PPC64DWARFRegisters = map[int16]int16{}
   296  
   297  func init() {
   298  	// f assigns dwarfregister[from:to] = (base):(to-from+base)
   299  	f := func(from, to, base int16) {
   300  		for r := int16(from); r <= to; r++ {
   301  			PPC64DWARFRegisters[r] = r - from + base
   302  		}
   303  	}
   304  	f(REG_R0, REG_R31, 0)
   305  	f(REG_F0, REG_F31, 32)
   306  	f(REG_V0, REG_V31, 77)
   307  	f(REG_CR0, REG_CR7, 68)
   308  
   309  	f(REG_VS0, REG_VS31, 32)  // overlaps F0-F31
   310  	f(REG_VS32, REG_VS63, 77) // overlaps V0-V31
   311  	PPC64DWARFRegisters[REG_LR] = 65
   312  	PPC64DWARFRegisters[REG_CTR] = 66
   313  	PPC64DWARFRegisters[REG_XER] = 76
   314  }
   315  
   316  /*
   317   * GENERAL:
   318   *
   319   * compiler allocates R3 up as temps
   320   * compiler allocates register variables R7-R27
   321   * compiler allocates external registers R30 down
   322   *
   323   * compiler allocates register variables F17-F26
   324   * compiler allocates external registers F26 down
   325   */
   326  const (
   327  	BIG = 32768 - 8
   328  )
   329  
   330  const (
   331  	/* mark flags */
   332  	LABEL    = 1 << 0
   333  	LEAF     = 1 << 1
   334  	FLOAT    = 1 << 2
   335  	BRANCH   = 1 << 3
   336  	LOAD     = 1 << 4
   337  	FCMP     = 1 << 5
   338  	SYNC     = 1 << 6
   339  	LIST     = 1 << 7
   340  	FOLL     = 1 << 8
   341  	NOSCHED  = 1 << 9
   342  	PFX_X64B = 1 << 10 // A prefixed instruction crossing a 64B boundary
   343  )
   344  
   345  // Values for use in branch instruction BC
   346  // BC B0,BI,label
   347  // BO is type of branch + likely bits described below
   348  // BI is CR value + branch type
   349  // ex: BEQ CR2,label is BC 12,10,label
   350  //   12 = BO_BCR
   351  //   10 = BI_CR2 + BI_EQ
   352  
   353  const (
   354  	BI_CR0 = 0
   355  	BI_CR1 = 4
   356  	BI_CR2 = 8
   357  	BI_CR3 = 12
   358  	BI_CR4 = 16
   359  	BI_CR5 = 20
   360  	BI_CR6 = 24
   361  	BI_CR7 = 28
   362  	BI_LT  = 0
   363  	BI_GT  = 1
   364  	BI_EQ  = 2
   365  	BI_OVF = 3
   366  )
   367  
   368  // Common values for the BO field.
   369  
   370  const (
   371  	BO_BCTR    = 16 // decrement ctr, branch on ctr != 0
   372  	BO_BCR     = 12 // branch on cr value
   373  	BO_BCRBCTR = 8  // decrement ctr, branch on ctr != 0 and cr value
   374  	BO_NOTBCR  = 4  // branch on not cr value
   375  )
   376  
   377  // Bit settings from the CR
   378  
   379  const (
   380  	C_COND_LT = iota // 0 result is negative
   381  	C_COND_GT        // 1 result is positive
   382  	C_COND_EQ        // 2 result is zero
   383  	C_COND_SO        // 3 summary overflow or FP compare w/ NaN
   384  )
   385  
   386  const (
   387  	C_NONE     = iota
   388  	C_REGP     /* An even numbered gpr which can be used a gpr pair argument */
   389  	C_REG      /* Any gpr register */
   390  	C_FREGP    /* An even numbered fpr which can be used a fpr pair argument */
   391  	C_FREG     /* Any fpr register */
   392  	C_VREG     /* Any vector register */
   393  	C_VSREGP   /* An even numbered vsx register which can be used as a vsx register pair argument */
   394  	C_VSREG    /* Any vector-scalar register */
   395  	C_CREG     /* The condition registor (CR) */
   396  	C_CRBIT    /* A single bit of the CR register (0-31) */
   397  	C_SPR      /* special processor register */
   398  	C_ZCON     /* The constant zero */
   399  	C_U1CON    /* 1 bit unsigned constant */
   400  	C_U2CON    /* 2 bit unsigned constant */
   401  	C_U3CON    /* 3 bit unsigned constant */
   402  	C_U4CON    /* 4 bit unsigned constant */
   403  	C_U5CON    /* 5 bit unsigned constant */
   404  	C_U8CON    /* 8 bit unsigned constant */
   405  	C_U15CON   /* 15 bit unsigned constant */
   406  	C_S16CON   /* 16 bit signed constant */
   407  	C_U16CON   /* 16 bit unsigned constant */
   408  	C_32S16CON /* Any 32 bit constant of the form 0x....0000, signed or unsigned */
   409  	C_32CON    /* Any constant which fits into 32 bits. Can be signed or unsigned */
   410  	C_S34CON   /* 34 bit signed constant */
   411  	C_64CON    /* Any constant which fits into 64 bits. Can be signed or unsigned */
   412  	C_SACON    /* $n(REG) where n <= int16 */
   413  	C_LACON    /* $n(REG) where n <= int32 */
   414  	C_DACON    /* $n(REG) where n <= int64 */
   415  	C_SBRA     /* A short offset argument to a branching instruction */
   416  	C_LBRA     /* A long offset argument to a branching instruction */
   417  	C_LBRAPIC  /* Like C_LBRA, but requires an extra NOP for potential TOC restore by the linker. */
   418  	C_ZOREG    /* An reg+reg memory arg, or a $0+reg memory op */
   419  	C_SOREG    /* An $n+reg memory arg where n is a 16 bit signed offset */
   420  	C_LOREG    /* An $n+reg memory arg where n is a 32 bit signed offset */
   421  	C_FPSCR    /* The fpscr register */
   422  	C_XER      /* The xer, holds the carry bit */
   423  	C_LR       /* The link register */
   424  	C_CTR      /* The count register */
   425  	C_ANY      /* Any argument */
   426  	C_GOK      /* A non-matched argument */
   427  	C_ADDR     /* A symbolic memory location */
   428  	C_TLS_LE   /* A thread local, local-exec, type memory arg */
   429  	C_TLS_IE   /* A thread local, initial-exec, type memory arg */
   430  	C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */
   431  
   432  	C_NCLASS /* must be the last */
   433  
   434  	/* Aliased names which should be cleaned up, or integrated. */
   435  	C_SCON   = C_U15CON
   436  	C_UCON   = C_32S16CON
   437  	C_ADDCON = C_S16CON
   438  	C_ANDCON = C_U16CON
   439  	C_LCON   = C_32CON
   440  
   441  	/* Aliased names which may be generated by ppc64map for the optab. */
   442  	C_S3216CON = C_32S16CON // TODO: these should be treated differently (e.g xoris vs addis)
   443  	C_U3216CON = C_32S16CON
   444  	C_S32CON   = C_32CON
   445  	C_U32CON   = C_32CON
   446  )
   447  
   448  const (
   449  	AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
   450  	AADDCC
   451  	AADDIS
   452  	AADDV
   453  	AADDVCC
   454  	AADDC
   455  	AADDCCC
   456  	AADDCV
   457  	AADDCVCC
   458  	AADDME
   459  	AADDMECC
   460  	AADDMEVCC
   461  	AADDMEV
   462  	AADDE
   463  	AADDECC
   464  	AADDEVCC
   465  	AADDEV
   466  	AADDZE
   467  	AADDZECC
   468  	AADDZEVCC
   469  	AADDZEV
   470  	AADDEX
   471  	AAND
   472  	AANDCC
   473  	AANDN
   474  	AANDNCC
   475  	AANDISCC
   476  	ABC
   477  	ABCL
   478  	ABEQ
   479  	ABGE // not LT = G/E/U
   480  	ABGT
   481  	ABLE // not GT = L/E/U
   482  	ABLT
   483  	ABNE // not EQ = L/G/U
   484  	ABVC // Unordered-clear
   485  	ABVS // Unordered-set
   486  	ACMP
   487  	ACMPU
   488  	ACMPEQB
   489  	ACNTLZW
   490  	ACNTLZWCC
   491  	ACRAND
   492  	ACRANDN
   493  	ACREQV
   494  	ACRNAND
   495  	ACRNOR
   496  	ACROR
   497  	ACRORN
   498  	ACRXOR
   499  	ADIVW
   500  	ADIVWCC
   501  	ADIVWVCC
   502  	ADIVWV
   503  	ADIVWU
   504  	ADIVWUCC
   505  	ADIVWUVCC
   506  	ADIVWUV
   507  	AMODUD
   508  	AMODUW
   509  	AMODSD
   510  	AMODSW
   511  	AEQV
   512  	AEQVCC
   513  	AEXTSB
   514  	AEXTSBCC
   515  	AEXTSH
   516  	AEXTSHCC
   517  	AFABS
   518  	AFABSCC
   519  	AFADD
   520  	AFADDCC
   521  	AFADDS
   522  	AFADDSCC
   523  	AFCMPO
   524  	AFCMPU
   525  	AFCTIW
   526  	AFCTIWCC
   527  	AFCTIWZ
   528  	AFCTIWZCC
   529  	AFDIV
   530  	AFDIVCC
   531  	AFDIVS
   532  	AFDIVSCC
   533  	AFMADD
   534  	AFMADDCC
   535  	AFMADDS
   536  	AFMADDSCC
   537  	AFMOVD
   538  	AFMOVDCC
   539  	AFMOVDU
   540  	AFMOVS
   541  	AFMOVSU
   542  	AFMOVSX
   543  	AFMOVSZ
   544  	AFMSUB
   545  	AFMSUBCC
   546  	AFMSUBS
   547  	AFMSUBSCC
   548  	AFMUL
   549  	AFMULCC
   550  	AFMULS
   551  	AFMULSCC
   552  	AFNABS
   553  	AFNABSCC
   554  	AFNEG
   555  	AFNEGCC
   556  	AFNMADD
   557  	AFNMADDCC
   558  	AFNMADDS
   559  	AFNMADDSCC
   560  	AFNMSUB
   561  	AFNMSUBCC
   562  	AFNMSUBS
   563  	AFNMSUBSCC
   564  	AFRSP
   565  	AFRSPCC
   566  	AFSUB
   567  	AFSUBCC
   568  	AFSUBS
   569  	AFSUBSCC
   570  	AISEL
   571  	AMOVMW
   572  	ALBAR
   573  	ALHAR
   574  	ALSW
   575  	ALWAR
   576  	ALWSYNC
   577  	AMOVDBR
   578  	AMOVWBR
   579  	AMOVB
   580  	AMOVBU
   581  	AMOVBZ
   582  	AMOVBZU
   583  	AMOVH
   584  	AMOVHBR
   585  	AMOVHU
   586  	AMOVHZ
   587  	AMOVHZU
   588  	AMOVW
   589  	AMOVWU
   590  	AMOVFL
   591  	AMOVCRFS
   592  	AMTFSB0
   593  	AMTFSB0CC
   594  	AMTFSB1
   595  	AMTFSB1CC
   596  	AMULHW
   597  	AMULHWCC
   598  	AMULHWU
   599  	AMULHWUCC
   600  	AMULLW
   601  	AMULLWCC
   602  	AMULLWVCC
   603  	AMULLWV
   604  	ANAND
   605  	ANANDCC
   606  	ANEG
   607  	ANEGCC
   608  	ANEGVCC
   609  	ANEGV
   610  	ANOR
   611  	ANORCC
   612  	AOR
   613  	AORCC
   614  	AORN
   615  	AORNCC
   616  	AORIS
   617  	AREM
   618  	AREMU
   619  	ARFI
   620  	ARLWMI
   621  	ARLWMICC
   622  	ARLWNM
   623  	ARLWNMCC
   624  	ACLRLSLWI
   625  	ASLW
   626  	ASLWCC
   627  	ASRW
   628  	ASRAW
   629  	ASRAWCC
   630  	ASRWCC
   631  	ASTBCCC
   632  	ASTHCCC
   633  	ASTSW
   634  	ASTWCCC
   635  	ASUB
   636  	ASUBCC
   637  	ASUBVCC
   638  	ASUBC
   639  	ASUBCCC
   640  	ASUBCV
   641  	ASUBCVCC
   642  	ASUBME
   643  	ASUBMECC
   644  	ASUBMEVCC
   645  	ASUBMEV
   646  	ASUBV
   647  	ASUBE
   648  	ASUBECC
   649  	ASUBEV
   650  	ASUBEVCC
   651  	ASUBZE
   652  	ASUBZECC
   653  	ASUBZEVCC
   654  	ASUBZEV
   655  	ASYNC
   656  	AXOR
   657  	AXORCC
   658  	AXORIS
   659  
   660  	ADCBF
   661  	ADCBI
   662  	ADCBST
   663  	ADCBT
   664  	ADCBTST
   665  	ADCBZ
   666  	AECIWX
   667  	AECOWX
   668  	AEIEIO
   669  	AICBI
   670  	AISYNC
   671  	APTESYNC
   672  	ATLBIE
   673  	ATLBIEL
   674  	ATLBSYNC
   675  	ATW
   676  
   677  	ASYSCALL
   678  	AWORD
   679  
   680  	ARFCI
   681  
   682  	AFCPSGN
   683  	AFCPSGNCC
   684  	/* optional on 32-bit */
   685  	AFRES
   686  	AFRESCC
   687  	AFRIM
   688  	AFRIMCC
   689  	AFRIP
   690  	AFRIPCC
   691  	AFRIZ
   692  	AFRIZCC
   693  	AFRIN
   694  	AFRINCC
   695  	AFRSQRTE
   696  	AFRSQRTECC
   697  	AFSEL
   698  	AFSELCC
   699  	AFSQRT
   700  	AFSQRTCC
   701  	AFSQRTS
   702  	AFSQRTSCC
   703  
   704  	/* 64-bit */
   705  
   706  	ACNTLZD
   707  	ACNTLZDCC
   708  	ACMPW /* CMP with L=0 */
   709  	ACMPWU
   710  	ACMPB
   711  	AFTDIV
   712  	AFTSQRT
   713  	ADIVD
   714  	ADIVDCC
   715  	ADIVDE
   716  	ADIVDECC
   717  	ADIVDEU
   718  	ADIVDEUCC
   719  	ADIVDVCC
   720  	ADIVDV
   721  	ADIVDU
   722  	ADIVDUCC
   723  	ADIVDUVCC
   724  	ADIVDUV
   725  	AEXTSW
   726  	AEXTSWCC
   727  	/* AFCFIW; AFCFIWCC */
   728  	AFCFID
   729  	AFCFIDCC
   730  	AFCFIDU
   731  	AFCFIDUCC
   732  	AFCFIDS
   733  	AFCFIDSCC
   734  	AFCTID
   735  	AFCTIDCC
   736  	AFCTIDZ
   737  	AFCTIDZCC
   738  	ALDAR
   739  	AMOVD
   740  	AMOVDU
   741  	AMOVWZ
   742  	AMOVWZU
   743  	AMULHD
   744  	AMULHDCC
   745  	AMULHDU
   746  	AMULHDUCC
   747  	AMULLD
   748  	AMULLDCC
   749  	AMULLDVCC
   750  	AMULLDV
   751  	ARFID
   752  	ARLDMI
   753  	ARLDMICC
   754  	ARLDIMI
   755  	ARLDIMICC
   756  	ARLDC
   757  	ARLDCCC
   758  	ARLDCR
   759  	ARLDCRCC
   760  	ARLDICR
   761  	ARLDICRCC
   762  	ARLDCL
   763  	ARLDCLCC
   764  	ARLDICL
   765  	ARLDICLCC
   766  	ARLDIC
   767  	ARLDICCC
   768  	ACLRLSLDI
   769  	AROTL
   770  	AROTLW
   771  	ASLBIA
   772  	ASLBIE
   773  	ASLBMFEE
   774  	ASLBMFEV
   775  	ASLBMTE
   776  	ASLD
   777  	ASLDCC
   778  	ASRD
   779  	ASRAD
   780  	ASRADCC
   781  	ASRDCC
   782  	AEXTSWSLI
   783  	AEXTSWSLICC
   784  	ASTDCCC
   785  	ATD
   786  
   787  	/* 64-bit pseudo operation */
   788  	ADWORD
   789  	AREMD
   790  	AREMDU
   791  
   792  	/* more 64-bit operations */
   793  	AHRFID
   794  	APOPCNTD
   795  	APOPCNTW
   796  	APOPCNTB
   797  	ACNTTZW
   798  	ACNTTZWCC
   799  	ACNTTZD
   800  	ACNTTZDCC
   801  	ACOPY
   802  	APASTECC
   803  	ADARN
   804  	ALDMX
   805  	AMADDHD
   806  	AMADDHDU
   807  	AMADDLD
   808  
   809  	/* Vector */
   810  	ALV
   811  	ALVEBX
   812  	ALVEHX
   813  	ALVEWX
   814  	ALVX
   815  	ALVXL
   816  	ALVSL
   817  	ALVSR
   818  	ASTV
   819  	ASTVEBX
   820  	ASTVEHX
   821  	ASTVEWX
   822  	ASTVX
   823  	ASTVXL
   824  	AVAND
   825  	AVANDC
   826  	AVNAND
   827  	AVOR
   828  	AVORC
   829  	AVNOR
   830  	AVXOR
   831  	AVEQV
   832  	AVADDUM
   833  	AVADDUBM
   834  	AVADDUHM
   835  	AVADDUWM
   836  	AVADDUDM
   837  	AVADDUQM
   838  	AVADDCU
   839  	AVADDCUQ
   840  	AVADDCUW
   841  	AVADDUS
   842  	AVADDUBS
   843  	AVADDUHS
   844  	AVADDUWS
   845  	AVADDSS
   846  	AVADDSBS
   847  	AVADDSHS
   848  	AVADDSWS
   849  	AVADDE
   850  	AVADDEUQM
   851  	AVADDECUQ
   852  	AVSUBUM
   853  	AVSUBUBM
   854  	AVSUBUHM
   855  	AVSUBUWM
   856  	AVSUBUDM
   857  	AVSUBUQM
   858  	AVSUBCU
   859  	AVSUBCUQ
   860  	AVSUBCUW
   861  	AVSUBUS
   862  	AVSUBUBS
   863  	AVSUBUHS
   864  	AVSUBUWS
   865  	AVSUBSS
   866  	AVSUBSBS
   867  	AVSUBSHS
   868  	AVSUBSWS
   869  	AVSUBE
   870  	AVSUBEUQM
   871  	AVSUBECUQ
   872  	AVMULESB
   873  	AVMULOSB
   874  	AVMULEUB
   875  	AVMULOUB
   876  	AVMULESH
   877  	AVMULOSH
   878  	AVMULEUH
   879  	AVMULOUH
   880  	AVMULESW
   881  	AVMULOSW
   882  	AVMULEUW
   883  	AVMULOUW
   884  	AVMULUWM
   885  	AVPMSUM
   886  	AVPMSUMB
   887  	AVPMSUMH
   888  	AVPMSUMW
   889  	AVPMSUMD
   890  	AVMSUMUDM
   891  	AVR
   892  	AVRLB
   893  	AVRLH
   894  	AVRLW
   895  	AVRLD
   896  	AVS
   897  	AVSLB
   898  	AVSLH
   899  	AVSLW
   900  	AVSL
   901  	AVSLO
   902  	AVSRB
   903  	AVSRH
   904  	AVSRW
   905  	AVSR
   906  	AVSRO
   907  	AVSLD
   908  	AVSRD
   909  	AVSA
   910  	AVSRAB
   911  	AVSRAH
   912  	AVSRAW
   913  	AVSRAD
   914  	AVSOI
   915  	AVSLDOI
   916  	AVCLZ
   917  	AVCLZB
   918  	AVCLZH
   919  	AVCLZW
   920  	AVCLZD
   921  	AVPOPCNT
   922  	AVPOPCNTB
   923  	AVPOPCNTH
   924  	AVPOPCNTW
   925  	AVPOPCNTD
   926  	AVCMPEQ
   927  	AVCMPEQUB
   928  	AVCMPEQUBCC
   929  	AVCMPEQUH
   930  	AVCMPEQUHCC
   931  	AVCMPEQUW
   932  	AVCMPEQUWCC
   933  	AVCMPEQUD
   934  	AVCMPEQUDCC
   935  	AVCMPGT
   936  	AVCMPGTUB
   937  	AVCMPGTUBCC
   938  	AVCMPGTUH
   939  	AVCMPGTUHCC
   940  	AVCMPGTUW
   941  	AVCMPGTUWCC
   942  	AVCMPGTUD
   943  	AVCMPGTUDCC
   944  	AVCMPGTSB
   945  	AVCMPGTSBCC
   946  	AVCMPGTSH
   947  	AVCMPGTSHCC
   948  	AVCMPGTSW
   949  	AVCMPGTSWCC
   950  	AVCMPGTSD
   951  	AVCMPGTSDCC
   952  	AVCMPNEZB
   953  	AVCMPNEZBCC
   954  	AVCMPNEB
   955  	AVCMPNEBCC
   956  	AVCMPNEH
   957  	AVCMPNEHCC
   958  	AVCMPNEW
   959  	AVCMPNEWCC
   960  	AVPERM
   961  	AVPERMXOR
   962  	AVPERMR
   963  	AVBPERMQ
   964  	AVBPERMD
   965  	AVSEL
   966  	AVSPLT
   967  	AVSPLTB
   968  	AVSPLTH
   969  	AVSPLTW
   970  	AVSPLTI
   971  	AVSPLTISB
   972  	AVSPLTISH
   973  	AVSPLTISW
   974  	AVCIPH
   975  	AVCIPHER
   976  	AVCIPHERLAST
   977  	AVNCIPH
   978  	AVNCIPHER
   979  	AVNCIPHERLAST
   980  	AVSBOX
   981  	AVSHASIGMA
   982  	AVSHASIGMAW
   983  	AVSHASIGMAD
   984  	AVMRGEW
   985  	AVMRGOW
   986  
   987  	/* VSX */
   988  	ALXV
   989  	ALXVL
   990  	ALXVLL
   991  	ALXVD2X
   992  	ALXVW4X
   993  	ALXVH8X
   994  	ALXVB16X
   995  	ALXVX
   996  	ALXVDSX
   997  	ASTXV
   998  	ASTXVL
   999  	ASTXVLL
  1000  	ASTXVD2X
  1001  	ASTXVW4X
  1002  	ASTXVH8X
  1003  	ASTXVB16X
  1004  	ASTXVX
  1005  	ALXSDX
  1006  	ASTXSDX
  1007  	ALXSIWAX
  1008  	ALXSIWZX
  1009  	ASTXSIWX
  1010  	AMFVSRD
  1011  	AMFFPRD
  1012  	AMFVRD
  1013  	AMFVSRWZ
  1014  	AMFVSRLD
  1015  	AMTVSRD
  1016  	AMTFPRD
  1017  	AMTVRD
  1018  	AMTVSRWA
  1019  	AMTVSRWZ
  1020  	AMTVSRDD
  1021  	AMTVSRWS
  1022  	AXXLAND
  1023  	AXXLANDC
  1024  	AXXLEQV
  1025  	AXXLNAND
  1026  	AXXLOR
  1027  	AXXLORC
  1028  	AXXLNOR
  1029  	AXXLORQ
  1030  	AXXLXOR
  1031  	AXXSEL
  1032  	AXXMRGHW
  1033  	AXXMRGLW
  1034  	AXXSPLT
  1035  	AXXSPLTW
  1036  	AXXSPLTIB
  1037  	AXXPERM
  1038  	AXXPERMDI
  1039  	AXXSLDWI
  1040  	AXXBRQ
  1041  	AXXBRD
  1042  	AXXBRW
  1043  	AXXBRH
  1044  	AXSCVDPSP
  1045  	AXSCVSPDP
  1046  	AXSCVDPSPN
  1047  	AXSCVSPDPN
  1048  	AXVCVDPSP
  1049  	AXVCVSPDP
  1050  	AXSCVDPSXDS
  1051  	AXSCVDPSXWS
  1052  	AXSCVDPUXDS
  1053  	AXSCVDPUXWS
  1054  	AXSCVSXDDP
  1055  	AXSCVUXDDP
  1056  	AXSCVSXDSP
  1057  	AXSCVUXDSP
  1058  	AXVCVDPSXDS
  1059  	AXVCVDPSXWS
  1060  	AXVCVDPUXDS
  1061  	AXVCVDPUXWS
  1062  	AXVCVSPSXDS
  1063  	AXVCVSPSXWS
  1064  	AXVCVSPUXDS
  1065  	AXVCVSPUXWS
  1066  	AXVCVSXDDP
  1067  	AXVCVSXWDP
  1068  	AXVCVUXDDP
  1069  	AXVCVUXWDP
  1070  	AXVCVSXDSP
  1071  	AXVCVSXWSP
  1072  	AXVCVUXDSP
  1073  	AXVCVUXWSP
  1074  
  1075  	/* ISA 3.1 opcodes */
  1076  	APNOP
  1077  
  1078  	ALAST
  1079  
  1080  	// aliases
  1081  	ABR = obj.AJMP
  1082  	ABL = obj.ACALL
  1083  )
  1084
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