cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import "cmd/internal/obj"
    32  
    33  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    34  
    35  const (
    36  	// Base register numberings.
    37  	REG_X0 = obj.RBaseRISCV + iota
    38  	REG_X1
    39  	REG_X2
    40  	REG_X3
    41  	REG_X4
    42  	REG_X5
    43  	REG_X6
    44  	REG_X7
    45  	REG_X8
    46  	REG_X9
    47  	REG_X10
    48  	REG_X11
    49  	REG_X12
    50  	REG_X13
    51  	REG_X14
    52  	REG_X15
    53  	REG_X16
    54  	REG_X17
    55  	REG_X18
    56  	REG_X19
    57  	REG_X20
    58  	REG_X21
    59  	REG_X22
    60  	REG_X23
    61  	REG_X24
    62  	REG_X25
    63  	REG_X26
    64  	REG_X27
    65  	REG_X28
    66  	REG_X29
    67  	REG_X30
    68  	REG_X31
    69  
    70  	// FP register numberings.
    71  	REG_F0
    72  	REG_F1
    73  	REG_F2
    74  	REG_F3
    75  	REG_F4
    76  	REG_F5
    77  	REG_F6
    78  	REG_F7
    79  	REG_F8
    80  	REG_F9
    81  	REG_F10
    82  	REG_F11
    83  	REG_F12
    84  	REG_F13
    85  	REG_F14
    86  	REG_F15
    87  	REG_F16
    88  	REG_F17
    89  	REG_F18
    90  	REG_F19
    91  	REG_F20
    92  	REG_F21
    93  	REG_F22
    94  	REG_F23
    95  	REG_F24
    96  	REG_F25
    97  	REG_F26
    98  	REG_F27
    99  	REG_F28
   100  	REG_F29
   101  	REG_F30
   102  	REG_F31
   103  
   104  	// This marks the end of the register numbering.
   105  	REG_END
   106  
   107  	// General registers reassigned to ABI names.
   108  	REG_ZERO = REG_X0
   109  	REG_RA   = REG_X1 // aka REG_LR
   110  	REG_SP   = REG_X2
   111  	REG_GP   = REG_X3 // aka REG_SB
   112  	REG_TP   = REG_X4
   113  	REG_T0   = REG_X5
   114  	REG_T1   = REG_X6
   115  	REG_T2   = REG_X7
   116  	REG_S0   = REG_X8
   117  	REG_S1   = REG_X9
   118  	REG_A0   = REG_X10
   119  	REG_A1   = REG_X11
   120  	REG_A2   = REG_X12
   121  	REG_A3   = REG_X13
   122  	REG_A4   = REG_X14
   123  	REG_A5   = REG_X15
   124  	REG_A6   = REG_X16
   125  	REG_A7   = REG_X17
   126  	REG_S2   = REG_X18
   127  	REG_S3   = REG_X19
   128  	REG_S4   = REG_X20 // aka REG_CTXT
   129  	REG_S5   = REG_X21
   130  	REG_S6   = REG_X22
   131  	REG_S7   = REG_X23
   132  	REG_S8   = REG_X24
   133  	REG_S9   = REG_X25
   134  	REG_S10  = REG_X26
   135  	REG_S11  = REG_X27 // aka REG_G
   136  	REG_T3   = REG_X28
   137  	REG_T4   = REG_X29
   138  	REG_T5   = REG_X30
   139  	REG_T6   = REG_X31 // aka REG_TMP
   140  
   141  	// Go runtime register names.
   142  	REG_G    = REG_S11 // G pointer.
   143  	REG_CTXT = REG_S4  // Context for closures.
   144  	REG_LR   = REG_RA  // Link register.
   145  	REG_TMP  = REG_T6  // Reserved for assembler use.
   146  
   147  	// ABI names for floating point registers.
   148  	REG_FT0  = REG_F0
   149  	REG_FT1  = REG_F1
   150  	REG_FT2  = REG_F2
   151  	REG_FT3  = REG_F3
   152  	REG_FT4  = REG_F4
   153  	REG_FT5  = REG_F5
   154  	REG_FT6  = REG_F6
   155  	REG_FT7  = REG_F7
   156  	REG_FS0  = REG_F8
   157  	REG_FS1  = REG_F9
   158  	REG_FA0  = REG_F10
   159  	REG_FA1  = REG_F11
   160  	REG_FA2  = REG_F12
   161  	REG_FA3  = REG_F13
   162  	REG_FA4  = REG_F14
   163  	REG_FA5  = REG_F15
   164  	REG_FA6  = REG_F16
   165  	REG_FA7  = REG_F17
   166  	REG_FS2  = REG_F18
   167  	REG_FS3  = REG_F19
   168  	REG_FS4  = REG_F20
   169  	REG_FS5  = REG_F21
   170  	REG_FS6  = REG_F22
   171  	REG_FS7  = REG_F23
   172  	REG_FS8  = REG_F24
   173  	REG_FS9  = REG_F25
   174  	REG_FS10 = REG_F26
   175  	REG_FS11 = REG_F27
   176  	REG_FT8  = REG_F28
   177  	REG_FT9  = REG_F29
   178  	REG_FT10 = REG_F30
   179  	REG_FT11 = REG_F31
   180  
   181  	// Names generated by the SSA compiler.
   182  	REGSP = REG_SP
   183  	REGG  = REG_G
   184  )
   185  
   186  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   187  var RISCV64DWARFRegisters = map[int16]int16{
   188  	// Integer Registers.
   189  	REG_X0:  0,
   190  	REG_X1:  1,
   191  	REG_X2:  2,
   192  	REG_X3:  3,
   193  	REG_X4:  4,
   194  	REG_X5:  5,
   195  	REG_X6:  6,
   196  	REG_X7:  7,
   197  	REG_X8:  8,
   198  	REG_X9:  9,
   199  	REG_X10: 10,
   200  	REG_X11: 11,
   201  	REG_X12: 12,
   202  	REG_X13: 13,
   203  	REG_X14: 14,
   204  	REG_X15: 15,
   205  	REG_X16: 16,
   206  	REG_X17: 17,
   207  	REG_X18: 18,
   208  	REG_X19: 19,
   209  	REG_X20: 20,
   210  	REG_X21: 21,
   211  	REG_X22: 22,
   212  	REG_X23: 23,
   213  	REG_X24: 24,
   214  	REG_X25: 25,
   215  	REG_X26: 26,
   216  	REG_X27: 27,
   217  	REG_X28: 28,
   218  	REG_X29: 29,
   219  	REG_X30: 30,
   220  	REG_X31: 31,
   221  
   222  	// Floating-Point Registers.
   223  	REG_F0:  32,
   224  	REG_F1:  33,
   225  	REG_F2:  34,
   226  	REG_F3:  35,
   227  	REG_F4:  36,
   228  	REG_F5:  37,
   229  	REG_F6:  38,
   230  	REG_F7:  39,
   231  	REG_F8:  40,
   232  	REG_F9:  41,
   233  	REG_F10: 42,
   234  	REG_F11: 43,
   235  	REG_F12: 44,
   236  	REG_F13: 45,
   237  	REG_F14: 46,
   238  	REG_F15: 47,
   239  	REG_F16: 48,
   240  	REG_F17: 49,
   241  	REG_F18: 50,
   242  	REG_F19: 51,
   243  	REG_F20: 52,
   244  	REG_F21: 53,
   245  	REG_F22: 54,
   246  	REG_F23: 55,
   247  	REG_F24: 56,
   248  	REG_F25: 57,
   249  	REG_F26: 58,
   250  	REG_F27: 59,
   251  	REG_F28: 60,
   252  	REG_F29: 61,
   253  	REG_F30: 62,
   254  	REG_F31: 63,
   255  }
   256  
   257  // Prog.Mark flags.
   258  const (
   259  	// USES_REG_TMP indicates that a machine instruction generated from the
   260  	// corresponding *obj.Prog uses the temporary register.
   261  	USES_REG_TMP = 1 << iota
   262  
   263  	// NEED_CALL_RELOC is set on JAL instructions to indicate that a
   264  	// R_RISCV_CALL relocation is needed.
   265  	NEED_CALL_RELOC
   266  
   267  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   268  	// it is the first instruction in an AUIPC + I-type pair that needs a
   269  	// R_RISCV_PCREL_ITYPE relocation.
   270  	NEED_PCREL_ITYPE_RELOC
   271  
   272  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   273  	// it is the first instruction in an AUIPC + S-type pair that needs a
   274  	// R_RISCV_PCREL_STYPE relocation.
   275  	NEED_PCREL_STYPE_RELOC
   276  )
   277  
   278  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   279  // from:
   280  //
   281  //    https://github.com/riscv/riscv-opcodes
   282  //
   283  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   284  //
   285  // See also "The RISC-V Instruction Set Manual" at:
   286  //
   287  //    https://riscv.org/specifications/
   288  //
   289  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   290  const (
   291  	// Unprivileged ISA (Document Version 20190608-Base-Ratified)
   292  
   293  	// 2.4: Integer Computational Instructions
   294  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   295  	ASLTI
   296  	ASLTIU
   297  	AANDI
   298  	AORI
   299  	AXORI
   300  	ASLLI
   301  	ASRLI
   302  	ASRAI
   303  	ALUI
   304  	AAUIPC
   305  	AADD
   306  	ASLT
   307  	ASLTU
   308  	AAND
   309  	AOR
   310  	AXOR
   311  	ASLL
   312  	ASRL
   313  	ASUB
   314  	ASRA
   315  
   316  	// The SLL/SRL/SRA instructions differ slightly between RV32 and RV64,
   317  	// hence there are pseudo-opcodes for the RV32 specific versions.
   318  	ASLLIRV32
   319  	ASRLIRV32
   320  	ASRAIRV32
   321  
   322  	// 2.5: Control Transfer Instructions
   323  	AJAL
   324  	AJALR
   325  	ABEQ
   326  	ABNE
   327  	ABLT
   328  	ABLTU
   329  	ABGE
   330  	ABGEU
   331  
   332  	// 2.6: Load and Store Instructions
   333  	ALW
   334  	ALWU
   335  	ALH
   336  	ALHU
   337  	ALB
   338  	ALBU
   339  	ASW
   340  	ASH
   341  	ASB
   342  
   343  	// 2.7: Memory Ordering Instructions
   344  	AFENCE
   345  	AFENCEI
   346  	AFENCETSO
   347  
   348  	// 5.2: Integer Computational Instructions (RV64I)
   349  	AADDIW
   350  	ASLLIW
   351  	ASRLIW
   352  	ASRAIW
   353  	AADDW
   354  	ASLLW
   355  	ASRLW
   356  	ASUBW
   357  	ASRAW
   358  
   359  	// 5.3: Load and Store Instructions (RV64I)
   360  	ALD
   361  	ASD
   362  
   363  	// 7.1: Multiplication Operations
   364  	AMUL
   365  	AMULH
   366  	AMULHU
   367  	AMULHSU
   368  	AMULW
   369  	ADIV
   370  	ADIVU
   371  	AREM
   372  	AREMU
   373  	ADIVW
   374  	ADIVUW
   375  	AREMW
   376  	AREMUW
   377  
   378  	// 8.2: Load-Reserved/Store-Conditional Instructions
   379  	ALRD
   380  	ASCD
   381  	ALRW
   382  	ASCW
   383  
   384  	// 8.3: Atomic Memory Operations
   385  	AAMOSWAPD
   386  	AAMOADDD
   387  	AAMOANDD
   388  	AAMOORD
   389  	AAMOXORD
   390  	AAMOMAXD
   391  	AAMOMAXUD
   392  	AAMOMIND
   393  	AAMOMINUD
   394  	AAMOSWAPW
   395  	AAMOADDW
   396  	AAMOANDW
   397  	AAMOORW
   398  	AAMOXORW
   399  	AAMOMAXW
   400  	AAMOMAXUW
   401  	AAMOMINW
   402  	AAMOMINUW
   403  
   404  	// 10.1: Base Counters and Timers
   405  	ARDCYCLE
   406  	ARDCYCLEH
   407  	ARDTIME
   408  	ARDTIMEH
   409  	ARDINSTRET
   410  	ARDINSTRETH
   411  
   412  	// 11.2: Floating-Point Control and Status Register
   413  	AFRCSR
   414  	AFSCSR
   415  	AFRRM
   416  	AFSRM
   417  	AFRFLAGS
   418  	AFSFLAGS
   419  	AFSRMI
   420  	AFSFLAGSI
   421  
   422  	// 11.5: Single-Precision Load and Store Instructions
   423  	AFLW
   424  	AFSW
   425  
   426  	// 11.6: Single-Precision Floating-Point Computational Instructions
   427  	AFADDS
   428  	AFSUBS
   429  	AFMULS
   430  	AFDIVS
   431  	AFMINS
   432  	AFMAXS
   433  	AFSQRTS
   434  	AFMADDS
   435  	AFMSUBS
   436  	AFNMADDS
   437  	AFNMSUBS
   438  
   439  	// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
   440  	AFCVTWS
   441  	AFCVTLS
   442  	AFCVTSW
   443  	AFCVTSL
   444  	AFCVTWUS
   445  	AFCVTLUS
   446  	AFCVTSWU
   447  	AFCVTSLU
   448  	AFSGNJS
   449  	AFSGNJNS
   450  	AFSGNJXS
   451  	AFMVXS
   452  	AFMVSX
   453  	AFMVXW
   454  	AFMVWX
   455  
   456  	// 11.8: Single-Precision Floating-Point Compare Instructions
   457  	AFEQS
   458  	AFLTS
   459  	AFLES
   460  
   461  	// 11.9: Single-Precision Floating-Point Classify Instruction
   462  	AFCLASSS
   463  
   464  	// 12.3: Double-Precision Load and Store Instructions
   465  	AFLD
   466  	AFSD
   467  
   468  	// 12.4: Double-Precision Floating-Point Computational Instructions
   469  	AFADDD
   470  	AFSUBD
   471  	AFMULD
   472  	AFDIVD
   473  	AFMIND
   474  	AFMAXD
   475  	AFSQRTD
   476  	AFMADDD
   477  	AFMSUBD
   478  	AFNMADDD
   479  	AFNMSUBD
   480  
   481  	// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
   482  	AFCVTWD
   483  	AFCVTLD
   484  	AFCVTDW
   485  	AFCVTDL
   486  	AFCVTWUD
   487  	AFCVTLUD
   488  	AFCVTDWU
   489  	AFCVTDLU
   490  	AFCVTSD
   491  	AFCVTDS
   492  	AFSGNJD
   493  	AFSGNJND
   494  	AFSGNJXD
   495  	AFMVXD
   496  	AFMVDX
   497  
   498  	// 12.6: Double-Precision Floating-Point Compare Instructions
   499  	AFEQD
   500  	AFLTD
   501  	AFLED
   502  
   503  	// 12.7: Double-Precision Floating-Point Classify Instruction
   504  	AFCLASSD
   505  
   506  	// 13.1 Quad-Precision Load and Store Instructions
   507  	AFLQ
   508  	AFSQ
   509  
   510  	// 13.2: Quad-Precision Computational Instructions
   511  	AFADDQ
   512  	AFSUBQ
   513  	AFMULQ
   514  	AFDIVQ
   515  	AFMINQ
   516  	AFMAXQ
   517  	AFSQRTQ
   518  	AFMADDQ
   519  	AFMSUBQ
   520  	AFNMADDQ
   521  	AFNMSUBQ
   522  
   523  	// 13.3 Quad-Precision Convert and Move Instructions
   524  	AFCVTWQ
   525  	AFCVTLQ
   526  	AFCVTSQ
   527  	AFCVTDQ
   528  	AFCVTQW
   529  	AFCVTQL
   530  	AFCVTQS
   531  	AFCVTQD
   532  	AFCVTWUQ
   533  	AFCVTLUQ
   534  	AFCVTQWU
   535  	AFCVTQLU
   536  	AFSGNJQ
   537  	AFSGNJNQ
   538  	AFSGNJXQ
   539  	AFMVXQ
   540  	AFMVQX
   541  
   542  	// 13.4 Quad-Precision Floating-Point Compare Instructions
   543  	AFEQQ
   544  	AFLEQ
   545  	AFLTQ
   546  
   547  	// 13.5 Quad-Precision Floating-Point Classify Instruction
   548  	AFCLASSQ
   549  
   550  	// Privileged ISA (Version 20190608-Priv-MSU-Ratified)
   551  
   552  	// 3.1.9: Instructions to Access CSRs
   553  	ACSRRW
   554  	ACSRRS
   555  	ACSRRC
   556  	ACSRRWI
   557  	ACSRRSI
   558  	ACSRRCI
   559  
   560  	// 3.2.1: Environment Call and Breakpoint
   561  	AECALL
   562  	ASCALL
   563  	AEBREAK
   564  	ASBREAK
   565  
   566  	// 3.2.2: Trap-Return Instructions
   567  	AMRET
   568  	ASRET
   569  	AURET
   570  	ADRET
   571  
   572  	// 3.2.3: Wait for Interrupt
   573  	AWFI
   574  
   575  	// 4.2.1: Supervisor Memory-Management Fence Instruction
   576  	ASFENCEVMA
   577  
   578  	// Hypervisor Memory-Management Instructions
   579  	AHFENCEGVMA
   580  	AHFENCEVVMA
   581  
   582  	// The escape hatch. Inserts a single 32-bit word.
   583  	AWORD
   584  
   585  	// Pseudo-instructions.  These get translated by the assembler into other
   586  	// instructions, based on their operands.
   587  	ABEQZ
   588  	ABGEZ
   589  	ABGT
   590  	ABGTU
   591  	ABGTZ
   592  	ABLE
   593  	ABLEU
   594  	ABLEZ
   595  	ABLTZ
   596  	ABNEZ
   597  	AFABSD
   598  	AFABSS
   599  	AFNEGD
   600  	AFNEGS
   601  	AFNED
   602  	AFNES
   603  	AMOV
   604  	AMOVB
   605  	AMOVBU
   606  	AMOVF
   607  	AMOVD
   608  	AMOVH
   609  	AMOVHU
   610  	AMOVW
   611  	AMOVWU
   612  	ANEG
   613  	ANEGW
   614  	ANOT
   615  	ASEQZ
   616  	ASNEZ
   617  
   618  	// End marker
   619  	ALAST
   620  )
   621  
   622  // All unary instructions which write to their arguments (as opposed to reading
   623  // from them) go here. The assembly parser uses this information to populate
   624  // its AST in a semantically reasonable way.
   625  //
   626  // Any instructions not listed here are assumed to either be non-unary or to read
   627  // from its argument.
   628  var unaryDst = map[obj.As]bool{
   629  	ARDCYCLE:    true,
   630  	ARDCYCLEH:   true,
   631  	ARDTIME:     true,
   632  	ARDTIMEH:    true,
   633  	ARDINSTRET:  true,
   634  	ARDINSTRETH: true,
   635  }
   636  
   637  // Instruction encoding masks.
   638  const (
   639  	// JTypeImmMask is a mask including only the immediate portion of
   640  	// J-type instructions.
   641  	JTypeImmMask = 0xfffff000
   642  
   643  	// ITypeImmMask is a mask including only the immediate portion of
   644  	// I-type instructions.
   645  	ITypeImmMask = 0xfff00000
   646  
   647  	// STypeImmMask is a mask including only the immediate portion of
   648  	// S-type instructions.
   649  	STypeImmMask = 0xfe000f80
   650  
   651  	// UTypeImmMask is a mask including only the immediate portion of
   652  	// U-type instructions.
   653  	UTypeImmMask = 0xfffff000
   654  )
   655
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