arg.go

     1  // Generated by ARM internal tool
     2  // DO NOT EDIT
     3  
     4  // Copyright 2017 The Go Authors. All rights reserved.
     5  // Use of this source code is governed by a BSD-style
     6  // license that can be found in the LICENSE file.
     7  
     8  package arm64asm
     9  
    10  // Naming for Go decoder arguments:
    11  //
    12  // - arg_Wd: a W register encoded in the Rd[4:0] field (31 is wzr)
    13  //
    14  // - arg_Xd: a X register encoded in the Rd[4:0] field (31 is xzr)
    15  //
    16  // - arg_Wds: a W register encoded in the Rd[4:0] field (31 is wsp)
    17  //
    18  // - arg_Xds: a X register encoded in the Rd[4:0] field (31 is sp)
    19  //
    20  // - arg_Wn: encoded in Rn[9:5]
    21  //
    22  // - arg_Wm: encoded in Rm[20:16]
    23  //
    24  // - arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
    25  //     a W register encoded in Rm with an extend encoded in option[15:13] and an amount
    26  //     encoded in imm3[12:10] in the range [0,4].
    27  //
    28  // - arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
    29  //     a W or X register encoded in Rm with an extend encoded in option[15:13] and an
    30  //     amount encoded in imm3[12:10] in the range [0,4]. If the extend is UXTX or SXTX,
    31  //     it's an X register else, it's a W register.
    32  //
    33  // - arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31:
    34  //     a W register encoded in Rm with a shift encoded in shift[23:22] and an amount
    35  //     encoded in imm6[15:10] in the range [0,31].
    36  //
    37  // - arg_IAddSub:
    38  //     An immediate for a add/sub instruction encoded in imm12[21:10] with an optional
    39  //     left shift of 12 encoded in shift[23:22].
    40  //
    41  // - arg_Rt_31_1__W_0__X_1:
    42  //     a W or X register encoded in Rt[4:0]. The width specifier is encoded in the field
    43  //     [31:31] (offset 31, bit count 1) and the register is W for 0 and X for 1.
    44  //
    45  // - arg_[s|u]label_FIELDS_POWER:
    46  //     a program label encoded as "FIELDS" times 2^POWER in the range [MIN, MAX] (determined
    47  //     by signd/unsigned, FIELDS and POWER), e.g.
    48  //       arg_slabel_imm14_2
    49  //       arg_slabel_imm19_2
    50  //       arg_slabel_imm26_2
    51  //       arg_slabel_immhi_immlo_0
    52  //       arg_slabel_immhi_immlo_12
    53  //
    54  // - arg_Xns_mem_post_imm7_8_signed:
    55  //     addressing mode of post-index with a base register: Xns and a signed offset encoded
    56  //     in the "imm7" field times 8
    57  //
    58  // - arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1:
    59  //     addressing mode of extended register with a base register: Xns, an offset register
    60  //     (<Wm>|<Xm>) with an extend encoded in option[15:13] and a shift amount encoded in
    61  //     S[12:12] in the range [0,3] (S=0:0, S=1:3).
    62  //
    63  // - arg_Xns_mem_optional_imm12_4_unsigned:
    64  //     addressing mode of unsigned offset with a base register: Xns and an optional unsigned
    65  //     offset encoded in the "imm12" field times 4
    66  //
    67  // - arg_Xns_mem_wb_imm7_4_signed:
    68  //     addressing mode of pre-index with a base register: Xns and the signed offset encoded
    69  //     in the "imm7" field times 4
    70  //
    71  // - arg_Xns_mem_post_size_1_8_unsigned__4_0__8_1__16_2__32_3:
    72  //     a post-index immediate offset, encoded in the "size" field. It can have the following values:
    73  //       #4 when size = 00
    74  //       #8 when size = 01
    75  //       #16 when size = 10
    76  //       #32 when size = 11
    77  //
    78  // - arg_immediate_0_127_CRm_op2:
    79  //     an immediate encoded in "CRm:op2" in the range 0 to 127
    80  //
    81  // - arg_immediate_bitmask_64_N_imms_immr:
    82  //     a bitmask immediate for 64-bit variant and encoded in "N:imms:immr"
    83  //
    84  // - arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms:
    85  //     an immediate for the <width> bitfield of SBFX 64-bit variant
    86  //
    87  // - arg_immediate_shift_32_implicit_inverse_imm16_hw:
    88  //     a 32-bit immediate of the bitwise inverse of which can be encoded in "imm16:hw"
    89  //
    90  // - arg_cond_[Not]AllowALNV_[Invert|Normal]:
    91  //     a standard condition, encoded in the "cond" field, excluding (NotAllow) AL and NV with
    92  //     its least significant bit [Yes|No] inverted, e.g.
    93  //       arg_cond_AllowALNV_Normal
    94  //       arg_cond_NotAllowALNV_Invert
    95  //
    96  // - arg_immediate_OptLSL_amount_16_0_48:
    97  //     An immediate for MOV[KNZ] instruction encoded in imm16[20:5] with an optional
    98  //     left shift of 16 in the range [0, 48] encoded in hw[22, 21]
    99  //
   100  // - arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
   101  //     the left shift amount, in the range 0 to the operand width in bits minus 1,
   102  //     encoded in the "immh:immb" field. It can have the following values:
   103  //       (UInt(immh:immb)-8) when immh = 0001
   104  //       (UInt(immh:immb)-16) when immh = 001x
   105  //       (UInt(immh:immb)-32) when immh = 01xx
   106  //       (UInt(immh:immb)-64) when immh = 1xxx
   107  //
   108  // - arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
   109  //     the right shift amount, in the range 1 to the destination operand width in
   110  //     bits, encoded in the "immh:immb" field. It can have the following values:
   111  //       (16-UInt(immh:immb)) when immh = 0001
   112  //       (32-UInt(immh:immb)) when immh = 001x
   113  //       (64-UInt(immh:immb)) when immh = 01xx
   114  //
   115  // - arg_immediate_8x8_a_b_c_d_e_f_g_h:
   116  //     a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
   117  //     encoded in "a:b:c:d:e:f:g:h".
   118  //
   119  // - arg_immediate_fbits_min_1_max_32_sub_64_scale:
   120  //     the number of bits after the binary point in the fixed-point destination,
   121  //     in the range 1 to 32, encoded as 64 minus "scale".
   122  //
   123  // - arg_immediate_floatzero: #0.0
   124  //
   125  // - arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h:
   126  //     a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision,
   127  //     encoded in "a:b:c:d:e:f:g:h"
   128  //
   129  // - arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8:
   130  //     the number of fractional bits, in the range 1 to the operand width, encoded
   131  //     in the "immh:immb" field. It can have the following values:
   132  //       (64-UInt(immh:immb)) when immh = 01xx
   133  //       (128-UInt(immh:immb)) when immh = 1xxx
   134  //
   135  // - arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10:
   136  //     the lowest numbered byte element to be extracted, encoded in the "Q:imm4" field.
   137  //     It can have the following values:
   138  //       imm4<2:0> when Q = 0, imm4<3> = 0
   139  //       imm4 when Q = 1, imm4<3> = x
   140  //
   141  // - arg_sysop_AT_SYS_CR_system:
   142  //     system operation for system instruction: AT encoded in the "op1:CRm<0>:op2" field
   143  //
   144  // - arg_prfop_Rt:
   145  //     prefectch operation encoded in the "Rt"
   146  //
   147  // - arg_sysreg_o0_op1_CRn_CRm_op2:
   148  //     system register name encoded in the "o0:op1:CRn:CRm:op2"
   149  //
   150  // - arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37:
   151  //     PSTATE field name encoded in the "op1:op2" field
   152  //
   153  // - arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
   154  //     one register with arrangement specifier encoded in the "size:Q" field which can have the following values:
   155  //       8B when size = 00, Q = 0
   156  //       16B when size = 00, Q = 1
   157  //       4H when size = 01, Q = 0
   158  //       8H when size = 01, Q = 1
   159  //       2S when size = 10, Q = 0
   160  //       4S when size = 10, Q = 1
   161  //       2D when size = 11, Q = 1
   162  //       The encoding size = 11, Q = 0 is reserved.
   163  //
   164  // - arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
   165  //     three registers with arrangement specifier encoded in the "size:Q" field which can have the following values:
   166  //       8B when size = 00, Q = 0
   167  //       16B when size = 00, Q = 1
   168  //       4H when size = 01, Q = 0
   169  //       8H when size = 01, Q = 1
   170  //       2S when size = 10, Q = 0
   171  //       4S when size = 10, Q = 1
   172  //       2D when size = 11, Q = 1
   173  //       The encoding size = 11, Q = 0 is reserved.
   174  //
   175  // - arg_Vt_1_arrangement_H_index__Q_S_size_1:
   176  //     one register with arrangement:H and element index encoded in "Q:S:size<1>".
   177  
   178  type instArg uint16
   179  
   180  const (
   181  	_ instArg = iota
   182  	arg_Bt
   183  	arg_Cm
   184  	arg_Cn
   185  	arg_cond_AllowALNV_Normal
   186  	arg_conditional
   187  	arg_cond_NotAllowALNV_Invert
   188  	arg_Da
   189  	arg_Dd
   190  	arg_Dm
   191  	arg_Dn
   192  	arg_Dt
   193  	arg_Dt2
   194  	arg_Hd
   195  	arg_Hn
   196  	arg_Ht
   197  	arg_IAddSub
   198  	arg_immediate_0_127_CRm_op2
   199  	arg_immediate_0_15_CRm
   200  	arg_immediate_0_15_nzcv
   201  	arg_immediate_0_31_imm5
   202  	arg_immediate_0_31_immr
   203  	arg_immediate_0_31_imms
   204  	arg_immediate_0_63_b5_b40
   205  	arg_immediate_0_63_immh_immb__UIntimmhimmb64_8
   206  	arg_immediate_0_63_immr
   207  	arg_immediate_0_63_imms
   208  	arg_immediate_0_65535_imm16
   209  	arg_immediate_0_7_op1
   210  	arg_immediate_0_7_op2
   211  	arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4
   212  	arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8
   213  	arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8
   214  	arg_immediate_0_width_size__8_0__16_1__32_2
   215  	arg_immediate_1_64_immh_immb__128UIntimmhimmb_8
   216  	arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4
   217  	arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4
   218  	arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8
   219  	arg_immediate_8x8_a_b_c_d_e_f_g_h
   220  	arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr
   221  	arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr
   222  	arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr
   223  	arg_immediate_BFI_BFM_32M_bitfield_width_32_imms
   224  	arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr
   225  	arg_immediate_BFI_BFM_64M_bitfield_width_64_imms
   226  	arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr
   227  	arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms
   228  	arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr
   229  	arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms
   230  	arg_immediate_bitmask_32_imms_immr
   231  	arg_immediate_bitmask_64_N_imms_immr
   232  	arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h
   233  	arg_immediate_exp_3_pre_4_imm8
   234  	arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8
   235  	arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8
   236  	arg_immediate_fbits_min_1_max_32_sub_64_scale
   237  	arg_immediate_fbits_min_1_max_64_sub_64_scale
   238  	arg_immediate_floatzero
   239  	arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10
   240  	arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr
   241  	arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr
   242  	arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr
   243  	arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr
   244  	arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1
   245  	arg_immediate_optional_0_15_CRm
   246  	arg_immediate_optional_0_65535_imm16
   247  	arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1
   248  	arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3
   249  	arg_immediate_OptLSL_amount_16_0_16
   250  	arg_immediate_OptLSL_amount_16_0_48
   251  	arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h
   252  	arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr
   253  	arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms
   254  	arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr
   255  	arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms
   256  	arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr
   257  	arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms
   258  	arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr
   259  	arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms
   260  	arg_immediate_shift_32_implicit_imm16_hw
   261  	arg_immediate_shift_32_implicit_inverse_imm16_hw
   262  	arg_immediate_shift_64_implicit_imm16_hw
   263  	arg_immediate_shift_64_implicit_inverse_imm16_hw
   264  	arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr
   265  	arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms
   266  	arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr
   267  	arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms
   268  	arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr
   269  	arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms
   270  	arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr
   271  	arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms
   272  	arg_immediate_zero
   273  	arg_option_DMB_BO_system_CRm
   274  	arg_option_DSB_BO_system_CRm
   275  	arg_option_ISB_BI_system_CRm
   276  	arg_prfop_Rt
   277  	arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37
   278  	arg_Qd
   279  	arg_Qn
   280  	arg_Qt
   281  	arg_Qt2
   282  	arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4
   283  	arg_Rn_16_5__W_1__W_2__W_4__X_8
   284  	arg_Rt_31_1__W_0__X_1
   285  	arg_Sa
   286  	arg_Sd
   287  	arg_slabel_imm14_2
   288  	arg_slabel_imm19_2
   289  	arg_slabel_imm26_2
   290  	arg_slabel_immhi_immlo_0
   291  	arg_slabel_immhi_immlo_12
   292  	arg_Sm
   293  	arg_Sn
   294  	arg_St
   295  	arg_St2
   296  	arg_sysop_AT_SYS_CR_system
   297  	arg_sysop_DC_SYS_CR_system
   298  	arg_sysop_IC_SYS_CR_system
   299  	arg_sysop_SYS_CR_system
   300  	arg_sysop_TLBI_SYS_CR_system
   301  	arg_sysreg_o0_op1_CRn_CRm_op2
   302  	arg_Vd_16_5__B_1__H_2__S_4__D_8
   303  	arg_Vd_19_4__B_1__H_2__S_4
   304  	arg_Vd_19_4__B_1__H_2__S_4__D_8
   305  	arg_Vd_19_4__D_8
   306  	arg_Vd_19_4__S_4__D_8
   307  	arg_Vd_22_1__S_0
   308  	arg_Vd_22_1__S_0__D_1
   309  	arg_Vd_22_1__S_1
   310  	arg_Vd_22_2__B_0__H_1__S_2
   311  	arg_Vd_22_2__B_0__H_1__S_2__D_3
   312  	arg_Vd_22_2__D_3
   313  	arg_Vd_22_2__H_0__S_1__D_2
   314  	arg_Vd_22_2__H_1__S_2
   315  	arg_Vd_22_2__S_1__D_2
   316  	arg_Vd_arrangement_16B
   317  	arg_Vd_arrangement_2D
   318  	arg_Vd_arrangement_4S
   319  	arg_Vd_arrangement_D_index__1
   320  	arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1
   321  	arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81
   322  	arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81
   323  	arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41
   324  	arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81
   325  	arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4
   326  	arg_Vd_arrangement_Q___2S_0__4S_1
   327  	arg_Vd_arrangement_Q___4H_0__8H_1
   328  	arg_Vd_arrangement_Q___8B_0__16B_1
   329  	arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11
   330  	arg_Vd_arrangement_size___4S_1__2D_2
   331  	arg_Vd_arrangement_size___8H_0__1Q_3
   332  	arg_Vd_arrangement_size___8H_0__4S_1__2D_2
   333  	arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21
   334  	arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21
   335  	arg_Vd_arrangement_size_Q___8B_00__16B_01
   336  	arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11
   337  	arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21
   338  	arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
   339  	arg_Vd_arrangement_sz___4S_0__2D_1
   340  	arg_Vd_arrangement_sz_Q___2S_00__4S_01
   341  	arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11
   342  	arg_Vd_arrangement_sz_Q___2S_10__4S_11
   343  	arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11
   344  	arg_Vm_22_1__S_0__D_1
   345  	arg_Vm_22_2__B_0__H_1__S_2__D_3
   346  	arg_Vm_22_2__D_3
   347  	arg_Vm_22_2__H_1__S_2
   348  	arg_Vm_arrangement_4S
   349  	arg_Vm_arrangement_Q___8B_0__16B_1
   350  	arg_Vm_arrangement_size___8H_0__4S_1__2D_2
   351  	arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1
   352  	arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21
   353  	arg_Vm_arrangement_size_Q___8B_00__16B_01
   354  	arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31
   355  	arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21
   356  	arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
   357  	arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11
   358  	arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1
   359  	arg_Vn_19_4__B_1__H_2__S_4__D_8
   360  	arg_Vn_19_4__D_8
   361  	arg_Vn_19_4__H_1__S_2__D_4
   362  	arg_Vn_19_4__S_4__D_8
   363  	arg_Vn_1_arrangement_16B
   364  	arg_Vn_22_1__D_1
   365  	arg_Vn_22_1__S_0__D_1
   366  	arg_Vn_22_2__B_0__H_1__S_2__D_3
   367  	arg_Vn_22_2__D_3
   368  	arg_Vn_22_2__H_0__S_1__D_2
   369  	arg_Vn_22_2__H_1__S_2
   370  	arg_Vn_2_arrangement_16B
   371  	arg_Vn_3_arrangement_16B
   372  	arg_Vn_4_arrangement_16B
   373  	arg_Vn_arrangement_16B
   374  	arg_Vn_arrangement_4S
   375  	arg_Vn_arrangement_D_index__1
   376  	arg_Vn_arrangement_D_index__imm5_1
   377  	arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1
   378  	arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1
   379  	arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1
   380  	arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1
   381  	arg_Vn_arrangement_imm5___D_8_index__imm5_1
   382  	arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81
   383  	arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41
   384  	arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81
   385  	arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4
   386  	arg_Vn_arrangement_Q___8B_0__16B_1
   387  	arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11
   388  	arg_Vn_arrangement_Q_sz___4S_10
   389  	arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1
   390  	arg_Vn_arrangement_size___2D_3
   391  	arg_Vn_arrangement_size___8H_0__4S_1__2D_2
   392  	arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21
   393  	arg_Vn_arrangement_size_Q___8B_00__16B_01
   394  	arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31
   395  	arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11
   396  	arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21
   397  	arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
   398  	arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21
   399  	arg_Vn_arrangement_sz___2D_1
   400  	arg_Vn_arrangement_sz___2S_0__2D_1
   401  	arg_Vn_arrangement_sz___4S_0__2D_1
   402  	arg_Vn_arrangement_sz_Q___2S_00__4S_01
   403  	arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11
   404  	arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11
   405  	arg_Vt_1_arrangement_B_index__Q_S_size_1
   406  	arg_Vt_1_arrangement_D_index__Q_1
   407  	arg_Vt_1_arrangement_H_index__Q_S_size_1
   408  	arg_Vt_1_arrangement_S_index__Q_S_1
   409  	arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
   410  	arg_Vt_2_arrangement_B_index__Q_S_size_1
   411  	arg_Vt_2_arrangement_D_index__Q_1
   412  	arg_Vt_2_arrangement_H_index__Q_S_size_1
   413  	arg_Vt_2_arrangement_S_index__Q_S_1
   414  	arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
   415  	arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
   416  	arg_Vt_3_arrangement_B_index__Q_S_size_1
   417  	arg_Vt_3_arrangement_D_index__Q_1
   418  	arg_Vt_3_arrangement_H_index__Q_S_size_1
   419  	arg_Vt_3_arrangement_S_index__Q_S_1
   420  	arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
   421  	arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
   422  	arg_Vt_4_arrangement_B_index__Q_S_size_1
   423  	arg_Vt_4_arrangement_D_index__Q_1
   424  	arg_Vt_4_arrangement_H_index__Q_S_size_1
   425  	arg_Vt_4_arrangement_S_index__Q_S_1
   426  	arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
   427  	arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
   428  	arg_Wa
   429  	arg_Wd
   430  	arg_Wds
   431  	arg_Wm
   432  	arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4
   433  	arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31
   434  	arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31
   435  	arg_Wn
   436  	arg_Wns
   437  	arg_Ws
   438  	arg_Wt
   439  	arg_Wt2
   440  	arg_Xa
   441  	arg_Xd
   442  	arg_Xds
   443  	arg_Xm
   444  	arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63
   445  	arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63
   446  	arg_Xn
   447  	arg_Xns
   448  	arg_Xns_mem
   449  	arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1
   450  	arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1
   451  	arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1
   452  	arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1
   453  	arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1
   454  	arg_Xns_mem_offset
   455  	arg_Xns_mem_optional_imm12_16_unsigned
   456  	arg_Xns_mem_optional_imm12_1_unsigned
   457  	arg_Xns_mem_optional_imm12_2_unsigned
   458  	arg_Xns_mem_optional_imm12_4_unsigned
   459  	arg_Xns_mem_optional_imm12_8_unsigned
   460  	arg_Xns_mem_optional_imm7_16_signed
   461  	arg_Xns_mem_optional_imm7_4_signed
   462  	arg_Xns_mem_optional_imm7_8_signed
   463  	arg_Xns_mem_optional_imm9_1_signed
   464  	arg_Xns_mem_post_fixedimm_1
   465  	arg_Xns_mem_post_fixedimm_12
   466  	arg_Xns_mem_post_fixedimm_16
   467  	arg_Xns_mem_post_fixedimm_2
   468  	arg_Xns_mem_post_fixedimm_24
   469  	arg_Xns_mem_post_fixedimm_3
   470  	arg_Xns_mem_post_fixedimm_32
   471  	arg_Xns_mem_post_fixedimm_4
   472  	arg_Xns_mem_post_fixedimm_6
   473  	arg_Xns_mem_post_fixedimm_8
   474  	arg_Xns_mem_post_imm7_16_signed
   475  	arg_Xns_mem_post_imm7_4_signed
   476  	arg_Xns_mem_post_imm7_8_signed
   477  	arg_Xns_mem_post_imm9_1_signed
   478  	arg_Xns_mem_post_Q__16_0__32_1
   479  	arg_Xns_mem_post_Q__24_0__48_1
   480  	arg_Xns_mem_post_Q__32_0__64_1
   481  	arg_Xns_mem_post_Q__8_0__16_1
   482  	arg_Xns_mem_post_size__1_0__2_1__4_2__8_3
   483  	arg_Xns_mem_post_size__2_0__4_1__8_2__16_3
   484  	arg_Xns_mem_post_size__3_0__6_1__12_2__24_3
   485  	arg_Xns_mem_post_size__4_0__8_1__16_2__32_3
   486  	arg_Xns_mem_post_Xm
   487  	arg_Xns_mem_wb_imm7_16_signed
   488  	arg_Xns_mem_wb_imm7_4_signed
   489  	arg_Xns_mem_wb_imm7_8_signed
   490  	arg_Xns_mem_wb_imm9_1_signed
   491  	arg_Xs
   492  	arg_Xt
   493  	arg_Xt2
   494  )
   495
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