Source file src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode.go

     1  // Copyright 2017 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package arm64asm
     6  
     7  import (
     8  	"encoding/binary"
     9  	"fmt"
    10  )
    11  
    12  type instArgs [5]instArg
    13  
    14  // An instFormat describes the format of an instruction encoding.
    15  // An instruction with 32-bit value x matches the format if x&mask == value
    16  // and the predicator: canDecode(x) return true.
    17  type instFormat struct {
    18  	mask  uint32
    19  	value uint32
    20  	op    Op
    21  	// args describe how to decode the instruction arguments.
    22  	// args is stored as a fixed-size array.
    23  	// if there are fewer than len(args) arguments, args[i] == 0 marks
    24  	// the end of the argument list.
    25  	args      instArgs
    26  	canDecode func(instr uint32) bool
    27  }
    28  
    29  var (
    30  	errShort   = fmt.Errorf("truncated instruction")
    31  	errUnknown = fmt.Errorf("unknown instruction")
    32  )
    33  
    34  var decoderCover []bool
    35  
    36  func init() {
    37  	decoderCover = make([]bool, len(instFormats))
    38  }
    39  
    40  // Decode decodes the 4 bytes in src as a single instruction.
    41  func Decode(src []byte) (inst Inst, err error) {
    42  	if len(src) < 4 {
    43  		return Inst{}, errShort
    44  	}
    45  
    46  	x := binary.LittleEndian.Uint32(src)
    47  
    48  Search:
    49  	for i := range instFormats {
    50  		f := &instFormats[i]
    51  		if x&f.mask != f.value {
    52  			continue
    53  		}
    54  		if f.canDecode != nil && !f.canDecode(x) {
    55  			continue
    56  		}
    57  		// Decode args.
    58  		var args Args
    59  		for j, aop := range f.args {
    60  			if aop == 0 {
    61  				break
    62  			}
    63  			arg := decodeArg(aop, x)
    64  			if arg == nil { // Cannot decode argument
    65  				continue Search
    66  			}
    67  			args[j] = arg
    68  		}
    69  		decoderCover[i] = true
    70  		inst = Inst{
    71  			Op:   f.op,
    72  			Args: args,
    73  			Enc:  x,
    74  		}
    75  		return inst, nil
    76  	}
    77  	return Inst{}, errUnknown
    78  }
    79  
    80  // decodeArg decodes the arg described by aop from the instruction bits x.
    81  // It returns nil if x cannot be decoded according to aop.
    82  func decodeArg(aop instArg, x uint32) Arg {
    83  	switch aop {
    84  	default:
    85  		return nil
    86  
    87  	case arg_Da:
    88  		return D0 + Reg((x>>10)&(1<<5-1))
    89  
    90  	case arg_Dd:
    91  		return D0 + Reg(x&(1<<5-1))
    92  
    93  	case arg_Dm:
    94  		return D0 + Reg((x>>16)&(1<<5-1))
    95  
    96  	case arg_Dn:
    97  		return D0 + Reg((x>>5)&(1<<5-1))
    98  
    99  	case arg_Hd:
   100  		return H0 + Reg(x&(1<<5-1))
   101  
   102  	case arg_Hn:
   103  		return H0 + Reg((x>>5)&(1<<5-1))
   104  
   105  	case arg_IAddSub:
   106  		imm12 := (x >> 10) & (1<<12 - 1)
   107  		shift := (x >> 22) & (1<<2 - 1)
   108  		if shift > 1 {
   109  			return nil
   110  		}
   111  		shift = shift * 12
   112  		return ImmShift{uint16(imm12), uint8(shift)}
   113  
   114  	case arg_Sa:
   115  		return S0 + Reg((x>>10)&(1<<5-1))
   116  
   117  	case arg_Sd:
   118  		return S0 + Reg(x&(1<<5-1))
   119  
   120  	case arg_Sm:
   121  		return S0 + Reg((x>>16)&(1<<5-1))
   122  
   123  	case arg_Sn:
   124  		return S0 + Reg((x>>5)&(1<<5-1))
   125  
   126  	case arg_Wa:
   127  		return W0 + Reg((x>>10)&(1<<5-1))
   128  
   129  	case arg_Wd:
   130  		return W0 + Reg(x&(1<<5-1))
   131  
   132  	case arg_Wds:
   133  		return RegSP(W0) + RegSP(x&(1<<5-1))
   134  
   135  	case arg_Wm:
   136  		return W0 + Reg((x>>16)&(1<<5-1))
   137  
   138  	case arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
   139  		return handle_ExtendedRegister(x, true)
   140  
   141  	case arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
   142  		return handle_ExtendedRegister(x, false)
   143  
   144  	case arg_Wn:
   145  		return W0 + Reg((x>>5)&(1<<5-1))
   146  
   147  	case arg_Wns:
   148  		return RegSP(W0) + RegSP((x>>5)&(1<<5-1))
   149  
   150  	case arg_Xa:
   151  		return X0 + Reg((x>>10)&(1<<5-1))
   152  
   153  	case arg_Xd:
   154  		return X0 + Reg(x&(1<<5-1))
   155  
   156  	case arg_Xds:
   157  		return RegSP(X0) + RegSP(x&(1<<5-1))
   158  
   159  	case arg_Xm:
   160  		return X0 + Reg((x>>16)&(1<<5-1))
   161  
   162  	case arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31:
   163  		return handle_ImmediateShiftedRegister(x, 31, true, false)
   164  
   165  	case arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31:
   166  		return handle_ImmediateShiftedRegister(x, 31, true, true)
   167  
   168  	case arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63:
   169  		return handle_ImmediateShiftedRegister(x, 63, false, false)
   170  
   171  	case arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63:
   172  		return handle_ImmediateShiftedRegister(x, 63, false, true)
   173  
   174  	case arg_Xn:
   175  		return X0 + Reg((x>>5)&(1<<5-1))
   176  
   177  	case arg_Xns:
   178  		return RegSP(X0) + RegSP((x>>5)&(1<<5-1))
   179  
   180  	case arg_slabel_imm14_2:
   181  		imm14 := ((x >> 5) & (1<<14 - 1))
   182  		return PCRel(((int64(imm14) << 2) << 48) >> 48)
   183  
   184  	case arg_slabel_imm19_2:
   185  		imm19 := ((x >> 5) & (1<<19 - 1))
   186  		return PCRel(((int64(imm19) << 2) << 43) >> 43)
   187  
   188  	case arg_slabel_imm26_2:
   189  		imm26 := (x & (1<<26 - 1))
   190  		return PCRel(((int64(imm26) << 2) << 36) >> 36)
   191  
   192  	case arg_slabel_immhi_immlo_0:
   193  		immhi := ((x >> 5) & (1<<19 - 1))
   194  		immlo := ((x >> 29) & (1<<2 - 1))
   195  		immhilo := (immhi)<<2 | immlo
   196  		return PCRel((int64(immhilo) << 43) >> 43)
   197  
   198  	case arg_slabel_immhi_immlo_12:
   199  		immhi := ((x >> 5) & (1<<19 - 1))
   200  		immlo := ((x >> 29) & (1<<2 - 1))
   201  		immhilo := (immhi)<<2 | immlo
   202  		return PCRel(((int64(immhilo) << 12) << 31) >> 31)
   203  
   204  	case arg_Xns_mem:
   205  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   206  		return MemImmediate{Rn, AddrOffset, 0}
   207  
   208  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1:
   209  		return handle_MemExtend(x, 1, false)
   210  
   211  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1:
   212  		return handle_MemExtend(x, 2, false)
   213  
   214  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1:
   215  		return handle_MemExtend(x, 3, false)
   216  
   217  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1:
   218  		return handle_MemExtend(x, 1, true)
   219  
   220  	case arg_Xns_mem_optional_imm12_1_unsigned:
   221  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   222  		imm12 := (x >> 10) & (1<<12 - 1)
   223  		return MemImmediate{Rn, AddrOffset, int32(imm12)}
   224  
   225  	case arg_Xns_mem_optional_imm12_2_unsigned:
   226  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   227  		imm12 := (x >> 10) & (1<<12 - 1)
   228  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 1)}
   229  
   230  	case arg_Xns_mem_optional_imm12_4_unsigned:
   231  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   232  		imm12 := (x >> 10) & (1<<12 - 1)
   233  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 2)}
   234  
   235  	case arg_Xns_mem_optional_imm12_8_unsigned:
   236  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   237  		imm12 := (x >> 10) & (1<<12 - 1)
   238  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 3)}
   239  
   240  	case arg_Xns_mem_optional_imm7_4_signed:
   241  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   242  		imm7 := (x >> 15) & (1<<7 - 1)
   243  		return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 2)) << 23) >> 23}
   244  
   245  	case arg_Xns_mem_optional_imm7_8_signed:
   246  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   247  		imm7 := (x >> 15) & (1<<7 - 1)
   248  		return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 3)) << 22) >> 22}
   249  
   250  	case arg_Xns_mem_optional_imm9_1_signed:
   251  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   252  		imm9 := (x >> 12) & (1<<9 - 1)
   253  		return MemImmediate{Rn, AddrOffset, (int32(imm9) << 23) >> 23}
   254  
   255  	case arg_Xns_mem_post_imm7_4_signed:
   256  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   257  		imm7 := (x >> 15) & (1<<7 - 1)
   258  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 2)) << 23) >> 23}
   259  
   260  	case arg_Xns_mem_post_imm7_8_signed:
   261  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   262  		imm7 := (x >> 15) & (1<<7 - 1)
   263  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 3)) << 22) >> 22}
   264  
   265  	case arg_Xns_mem_post_imm9_1_signed:
   266  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   267  		imm9 := (x >> 12) & (1<<9 - 1)
   268  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm9)) << 23) >> 23}
   269  
   270  	case arg_Xns_mem_wb_imm7_4_signed:
   271  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   272  		imm7 := (x >> 15) & (1<<7 - 1)
   273  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 2)) << 23) >> 23}
   274  
   275  	case arg_Xns_mem_wb_imm7_8_signed:
   276  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   277  		imm7 := (x >> 15) & (1<<7 - 1)
   278  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 3)) << 22) >> 22}
   279  
   280  	case arg_Xns_mem_wb_imm9_1_signed:
   281  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   282  		imm9 := (x >> 12) & (1<<9 - 1)
   283  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm9)) << 23) >> 23}
   284  
   285  	case arg_Ws:
   286  		return W0 + Reg((x>>16)&(1<<5-1))
   287  
   288  	case arg_Wt:
   289  		return W0 + Reg(x&(1<<5-1))
   290  
   291  	case arg_Wt2:
   292  		return W0 + Reg((x>>10)&(1<<5-1))
   293  
   294  	case arg_Xs:
   295  		return X0 + Reg((x>>16)&(1<<5-1))
   296  
   297  	case arg_Xt:
   298  		return X0 + Reg(x&(1<<5-1))
   299  
   300  	case arg_Xt2:
   301  		return X0 + Reg((x>>10)&(1<<5-1))
   302  
   303  	case arg_immediate_0_127_CRm_op2:
   304  		crm_op2 := (x >> 5) & (1<<7 - 1)
   305  		return Imm_hint(crm_op2)
   306  
   307  	case arg_immediate_0_15_CRm:
   308  		crm := (x >> 8) & (1<<4 - 1)
   309  		return Imm{crm, false}
   310  
   311  	case arg_immediate_0_15_nzcv:
   312  		nzcv := x & (1<<4 - 1)
   313  		return Imm{nzcv, false}
   314  
   315  	case arg_immediate_0_31_imm5:
   316  		imm5 := (x >> 16) & (1<<5 - 1)
   317  		return Imm{imm5, false}
   318  
   319  	case arg_immediate_0_31_immr:
   320  		immr := (x >> 16) & (1<<6 - 1)
   321  		if immr > 31 {
   322  			return nil
   323  		}
   324  		return Imm{immr, false}
   325  
   326  	case arg_immediate_0_31_imms:
   327  		imms := (x >> 10) & (1<<6 - 1)
   328  		if imms > 31 {
   329  			return nil
   330  		}
   331  		return Imm{imms, true}
   332  
   333  	case arg_immediate_0_63_b5_b40:
   334  		b5 := (x >> 31) & 1
   335  		b40 := (x >> 19) & (1<<5 - 1)
   336  		return Imm{(b5 << 5) | b40, true}
   337  
   338  	case arg_immediate_0_63_immr:
   339  		immr := (x >> 16) & (1<<6 - 1)
   340  		return Imm{immr, false}
   341  
   342  	case arg_immediate_0_63_imms:
   343  		imms := (x >> 10) & (1<<6 - 1)
   344  		return Imm{imms, true}
   345  
   346  	case arg_immediate_0_65535_imm16:
   347  		imm16 := (x >> 5) & (1<<16 - 1)
   348  		return Imm{imm16, false}
   349  
   350  	case arg_immediate_0_7_op1:
   351  		op1 := (x >> 16) & (1<<3 - 1)
   352  		return Imm{op1, true}
   353  
   354  	case arg_immediate_0_7_op2:
   355  		op2 := (x >> 5) & (1<<3 - 1)
   356  		return Imm{op2, true}
   357  
   358  	case arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr:
   359  		immr := (x >> 16) & (1<<6 - 1)
   360  		if immr > 31 {
   361  			return nil
   362  		}
   363  		return Imm{immr, true}
   364  
   365  	case arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr:
   366  		immr := (x >> 16) & (1<<6 - 1)
   367  		return Imm{immr, true}
   368  
   369  	case arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr:
   370  		immr := (x >> 16) & (1<<6 - 1)
   371  		if immr > 31 {
   372  			return nil
   373  		}
   374  		return Imm{32 - immr, true}
   375  
   376  	case arg_immediate_BFI_BFM_32M_bitfield_width_32_imms:
   377  		imms := (x >> 10) & (1<<6 - 1)
   378  		if imms > 31 {
   379  			return nil
   380  		}
   381  		return Imm{imms + 1, true}
   382  
   383  	case arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr:
   384  		immr := (x >> 16) & (1<<6 - 1)
   385  		return Imm{64 - immr, true}
   386  
   387  	case arg_immediate_BFI_BFM_64M_bitfield_width_64_imms:
   388  		imms := (x >> 10) & (1<<6 - 1)
   389  		return Imm{imms + 1, true}
   390  
   391  	case arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr:
   392  		immr := (x >> 16) & (1<<6 - 1)
   393  		if immr > 31 {
   394  			return nil
   395  		}
   396  		return Imm{immr, true}
   397  
   398  	case arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms:
   399  		immr := (x >> 16) & (1<<6 - 1)
   400  		imms := (x >> 10) & (1<<6 - 1)
   401  		width := imms - immr + 1
   402  		if width < 1 || width > 32-immr {
   403  			return nil
   404  		}
   405  		return Imm{width, true}
   406  
   407  	case arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr:
   408  		immr := (x >> 16) & (1<<6 - 1)
   409  		return Imm{immr, true}
   410  
   411  	case arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms:
   412  		immr := (x >> 16) & (1<<6 - 1)
   413  		imms := (x >> 10) & (1<<6 - 1)
   414  		width := imms - immr + 1
   415  		if width < 1 || width > 64-immr {
   416  			return nil
   417  		}
   418  		return Imm{width, true}
   419  
   420  	case arg_immediate_bitmask_32_imms_immr:
   421  		return handle_bitmasks(x, 32)
   422  
   423  	case arg_immediate_bitmask_64_N_imms_immr:
   424  		return handle_bitmasks(x, 64)
   425  
   426  	case arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr:
   427  		imms := (x >> 10) & (1<<6 - 1)
   428  		shift := 31 - imms
   429  		if shift > 31 {
   430  			return nil
   431  		}
   432  		return Imm{shift, true}
   433  
   434  	case arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr:
   435  		imms := (x >> 10) & (1<<6 - 1)
   436  		shift := 63 - imms
   437  		if shift > 63 {
   438  			return nil
   439  		}
   440  		return Imm{shift, true}
   441  
   442  	case arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr:
   443  		immr := (x >> 16) & (1<<6 - 1)
   444  		if immr > 31 {
   445  			return nil
   446  		}
   447  		return Imm{immr, true}
   448  
   449  	case arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr:
   450  		immr := (x >> 16) & (1<<6 - 1)
   451  		return Imm{immr, true}
   452  
   453  	case arg_immediate_optional_0_15_CRm:
   454  		crm := (x >> 8) & (1<<4 - 1)
   455  		return Imm_clrex(crm)
   456  
   457  	case arg_immediate_optional_0_65535_imm16:
   458  		imm16 := (x >> 5) & (1<<16 - 1)
   459  		return Imm_dcps(imm16)
   460  
   461  	case arg_immediate_OptLSL_amount_16_0_16:
   462  		imm16 := (x >> 5) & (1<<16 - 1)
   463  		hw := (x >> 21) & (1<<2 - 1)
   464  		shift := hw * 16
   465  		if shift > 16 {
   466  			return nil
   467  		}
   468  		return ImmShift{uint16(imm16), uint8(shift)}
   469  
   470  	case arg_immediate_OptLSL_amount_16_0_48:
   471  		imm16 := (x >> 5) & (1<<16 - 1)
   472  		hw := (x >> 21) & (1<<2 - 1)
   473  		shift := hw * 16
   474  		return ImmShift{uint16(imm16), uint8(shift)}
   475  
   476  	case arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr:
   477  		immr := (x >> 16) & (1<<6 - 1)
   478  		if immr > 31 {
   479  			return nil
   480  		}
   481  		return Imm{32 - immr, true}
   482  
   483  	case arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms:
   484  		imms := (x >> 10) & (1<<6 - 1)
   485  		if imms > 31 {
   486  			return nil
   487  		}
   488  		return Imm{imms + 1, true}
   489  
   490  	case arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr:
   491  		immr := (x >> 16) & (1<<6 - 1)
   492  		return Imm{64 - immr, true}
   493  
   494  	case arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms:
   495  		imms := (x >> 10) & (1<<6 - 1)
   496  		return Imm{imms + 1, true}
   497  
   498  	case arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr:
   499  		immr := (x >> 16) & (1<<6 - 1)
   500  		if immr > 31 {
   501  			return nil
   502  		}
   503  		return Imm{immr, true}
   504  
   505  	case arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms:
   506  		immr := (x >> 16) & (1<<6 - 1)
   507  		imms := (x >> 10) & (1<<6 - 1)
   508  		width := imms - immr + 1
   509  		if width < 1 || width > 32-immr {
   510  			return nil
   511  		}
   512  		return Imm{width, true}
   513  
   514  	case arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr:
   515  		immr := (x >> 16) & (1<<6 - 1)
   516  		return Imm{immr, true}
   517  
   518  	case arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms:
   519  		immr := (x >> 16) & (1<<6 - 1)
   520  		imms := (x >> 10) & (1<<6 - 1)
   521  		width := imms - immr + 1
   522  		if width < 1 || width > 64-immr {
   523  			return nil
   524  		}
   525  		return Imm{width, true}
   526  
   527  	case arg_immediate_shift_32_implicit_imm16_hw:
   528  		imm16 := (x >> 5) & (1<<16 - 1)
   529  		hw := (x >> 21) & (1<<2 - 1)
   530  		shift := hw * 16
   531  		if shift > 16 {
   532  			return nil
   533  		}
   534  		result := uint32(imm16) << shift
   535  		return Imm{result, false}
   536  
   537  	case arg_immediate_shift_32_implicit_inverse_imm16_hw:
   538  		imm16 := (x >> 5) & (1<<16 - 1)
   539  		hw := (x >> 21) & (1<<2 - 1)
   540  		shift := hw * 16
   541  		if shift > 16 {
   542  			return nil
   543  		}
   544  		result := uint32(imm16) << shift
   545  		return Imm{^result, false}
   546  
   547  	case arg_immediate_shift_64_implicit_imm16_hw:
   548  		imm16 := (x >> 5) & (1<<16 - 1)
   549  		hw := (x >> 21) & (1<<2 - 1)
   550  		shift := hw * 16
   551  		result := uint64(imm16) << shift
   552  		return Imm64{result, false}
   553  
   554  	case arg_immediate_shift_64_implicit_inverse_imm16_hw:
   555  		imm16 := (x >> 5) & (1<<16 - 1)
   556  		hw := (x >> 21) & (1<<2 - 1)
   557  		shift := hw * 16
   558  		result := uint64(imm16) << shift
   559  		return Imm64{^result, false}
   560  
   561  	case arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr:
   562  		immr := (x >> 16) & (1<<6 - 1)
   563  		if immr > 31 {
   564  			return nil
   565  		}
   566  		return Imm{32 - immr, true}
   567  
   568  	case arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms:
   569  		imms := (x >> 10) & (1<<6 - 1)
   570  		if imms > 31 {
   571  			return nil
   572  		}
   573  		return Imm{imms + 1, true}
   574  
   575  	case arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr:
   576  		immr := (x >> 16) & (1<<6 - 1)
   577  		return Imm{64 - immr, true}
   578  
   579  	case arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms:
   580  		imms := (x >> 10) & (1<<6 - 1)
   581  		return Imm{imms + 1, true}
   582  
   583  	case arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr:
   584  		immr := (x >> 16) & (1<<6 - 1)
   585  		if immr > 31 {
   586  			return nil
   587  		}
   588  		return Imm{immr, true}
   589  
   590  	case arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms:
   591  		immr := (x >> 16) & (1<<6 - 1)
   592  		imms := (x >> 10) & (1<<6 - 1)
   593  		width := imms - immr + 1
   594  		if width < 1 || width > 32-immr {
   595  			return nil
   596  		}
   597  		return Imm{width, true}
   598  
   599  	case arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr:
   600  		immr := (x >> 16) & (1<<6 - 1)
   601  		return Imm{immr, true}
   602  
   603  	case arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms:
   604  		immr := (x >> 16) & (1<<6 - 1)
   605  		imms := (x >> 10) & (1<<6 - 1)
   606  		width := imms - immr + 1
   607  		if width < 1 || width > 64-immr {
   608  			return nil
   609  		}
   610  		return Imm{width, true}
   611  
   612  	case arg_Rt_31_1__W_0__X_1:
   613  		b5 := (x >> 31) & 1
   614  		Rt := x & (1<<5 - 1)
   615  		if b5 == 0 {
   616  			return W0 + Reg(Rt)
   617  		} else {
   618  			return X0 + Reg(Rt)
   619  		}
   620  
   621  	case arg_cond_AllowALNV_Normal:
   622  		cond := (x >> 12) & (1<<4 - 1)
   623  		return Cond{uint8(cond), false}
   624  
   625  	case arg_conditional:
   626  		cond := x & (1<<4 - 1)
   627  		return Cond{uint8(cond), false}
   628  
   629  	case arg_cond_NotAllowALNV_Invert:
   630  		cond := (x >> 12) & (1<<4 - 1)
   631  		if (cond >> 1) == 7 {
   632  			return nil
   633  		}
   634  		return Cond{uint8(cond), true}
   635  
   636  	case arg_Cm:
   637  		CRm := (x >> 8) & (1<<4 - 1)
   638  		return Imm_c(CRm)
   639  
   640  	case arg_Cn:
   641  		CRn := (x >> 12) & (1<<4 - 1)
   642  		return Imm_c(CRn)
   643  
   644  	case arg_option_DMB_BO_system_CRm:
   645  		CRm := (x >> 8) & (1<<4 - 1)
   646  		return Imm_option(CRm)
   647  
   648  	case arg_option_DSB_BO_system_CRm:
   649  		CRm := (x >> 8) & (1<<4 - 1)
   650  		return Imm_option(CRm)
   651  
   652  	case arg_option_ISB_BI_system_CRm:
   653  		CRm := (x >> 8) & (1<<4 - 1)
   654  		if CRm == 15 {
   655  			return Imm_option(CRm)
   656  		}
   657  		return Imm{CRm, false}
   658  
   659  	case arg_prfop_Rt:
   660  		Rt := x & (1<<5 - 1)
   661  		return Imm_prfop(Rt)
   662  
   663  	case arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37:
   664  		op1 := (x >> 16) & (1<<3 - 1)
   665  		op2 := (x >> 5) & (1<<3 - 1)
   666  		if (op1 == 0) && (op2 == 5) {
   667  			return SPSel
   668  		} else if (op1 == 3) && (op2 == 6) {
   669  			return DAIFSet
   670  		} else if (op1 == 3) && (op2 == 7) {
   671  			return DAIFClr
   672  		}
   673  		return nil
   674  
   675  	case arg_sysreg_o0_op1_CRn_CRm_op2:
   676  		op0 := (x >> 19) & (1<<2 - 1)
   677  		op1 := (x >> 16) & (1<<3 - 1)
   678  		CRn := (x >> 12) & (1<<4 - 1)
   679  		CRm := (x >> 8) & (1<<4 - 1)
   680  		op2 := (x >> 5) & (1<<3 - 1)
   681  		return Systemreg{uint8(op0), uint8(op1), uint8(CRn), uint8(CRm), uint8(op2)}
   682  
   683  	case arg_sysop_AT_SYS_CR_system:
   684  		//TODO: system instruction
   685  		return nil
   686  
   687  	case arg_sysop_DC_SYS_CR_system:
   688  		//TODO: system instruction
   689  		return nil
   690  
   691  	case arg_sysop_SYS_CR_system:
   692  		//TODO: system instruction
   693  		return nil
   694  
   695  	case arg_sysop_TLBI_SYS_CR_system:
   696  		//TODO: system instruction
   697  		return nil
   698  
   699  	case arg_Bt:
   700  		return B0 + Reg(x&(1<<5-1))
   701  
   702  	case arg_Dt:
   703  		return D0 + Reg(x&(1<<5-1))
   704  
   705  	case arg_Dt2:
   706  		return D0 + Reg((x>>10)&(1<<5-1))
   707  
   708  	case arg_Ht:
   709  		return H0 + Reg(x&(1<<5-1))
   710  
   711  	case arg_immediate_0_63_immh_immb__UIntimmhimmb64_8:
   712  		immh := (x >> 19) & (1<<4 - 1)
   713  		if (immh & 8) == 0 {
   714  			return nil
   715  		}
   716  		immb := (x >> 16) & (1<<3 - 1)
   717  		return Imm{(immh << 3) + immb - 64, true}
   718  
   719  	case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4:
   720  		immh := (x >> 19) & (1<<4 - 1)
   721  		immb := (x >> 16) & (1<<3 - 1)
   722  		if immh == 1 {
   723  			return Imm{(immh << 3) + immb - 8, true}
   724  		} else if (immh >> 1) == 1 {
   725  			return Imm{(immh << 3) + immb - 16, true}
   726  		} else if (immh >> 2) == 1 {
   727  			return Imm{(immh << 3) + immb - 32, true}
   728  		} else {
   729  			return nil
   730  		}
   731  
   732  	case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
   733  		fallthrough
   734  
   735  	case arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
   736  		immh := (x >> 19) & (1<<4 - 1)
   737  		immb := (x >> 16) & (1<<3 - 1)
   738  		if immh == 1 {
   739  			return Imm{(immh << 3) + immb - 8, true}
   740  		} else if (immh >> 1) == 1 {
   741  			return Imm{(immh << 3) + immb - 16, true}
   742  		} else if (immh >> 2) == 1 {
   743  			return Imm{(immh << 3) + immb - 32, true}
   744  		} else if (immh >> 3) == 1 {
   745  			return Imm{(immh << 3) + immb - 64, true}
   746  		} else {
   747  			return nil
   748  		}
   749  
   750  	case arg_immediate_0_width_size__8_0__16_1__32_2:
   751  		size := (x >> 22) & (1<<2 - 1)
   752  		switch size {
   753  		case 0:
   754  			return Imm{8, true}
   755  		case 1:
   756  			return Imm{16, true}
   757  		case 2:
   758  			return Imm{32, true}
   759  		default:
   760  			return nil
   761  		}
   762  
   763  	case arg_immediate_1_64_immh_immb__128UIntimmhimmb_8:
   764  		immh := (x >> 19) & (1<<4 - 1)
   765  		if (immh & 8) == 0 {
   766  			return nil
   767  		}
   768  		immb := (x >> 16) & (1<<3 - 1)
   769  		return Imm{128 - ((immh << 3) + immb), true}
   770  
   771  	case arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
   772  		fallthrough
   773  
   774  	case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
   775  		immh := (x >> 19) & (1<<4 - 1)
   776  		immb := (x >> 16) & (1<<3 - 1)
   777  		if immh == 1 {
   778  			return Imm{16 - ((immh << 3) + immb), true}
   779  		} else if (immh >> 1) == 1 {
   780  			return Imm{32 - ((immh << 3) + immb), true}
   781  		} else if (immh >> 2) == 1 {
   782  			return Imm{64 - ((immh << 3) + immb), true}
   783  		} else {
   784  			return nil
   785  		}
   786  
   787  	case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8:
   788  		immh := (x >> 19) & (1<<4 - 1)
   789  		immb := (x >> 16) & (1<<3 - 1)
   790  		if immh == 1 {
   791  			return Imm{16 - ((immh << 3) + immb), true}
   792  		} else if (immh >> 1) == 1 {
   793  			return Imm{32 - ((immh << 3) + immb), true}
   794  		} else if (immh >> 2) == 1 {
   795  			return Imm{64 - ((immh << 3) + immb), true}
   796  		} else if (immh >> 3) == 1 {
   797  			return Imm{128 - ((immh << 3) + immb), true}
   798  		} else {
   799  			return nil
   800  		}
   801  
   802  	case arg_immediate_8x8_a_b_c_d_e_f_g_h:
   803  		var imm uint64
   804  		if x&(1<<5) != 0 {
   805  			imm = (1 << 8) - 1
   806  		} else {
   807  			imm = 0
   808  		}
   809  		if x&(1<<6) != 0 {
   810  			imm += ((1 << 8) - 1) << 8
   811  		}
   812  		if x&(1<<7) != 0 {
   813  			imm += ((1 << 8) - 1) << 16
   814  		}
   815  		if x&(1<<8) != 0 {
   816  			imm += ((1 << 8) - 1) << 24
   817  		}
   818  		if x&(1<<9) != 0 {
   819  			imm += ((1 << 8) - 1) << 32
   820  		}
   821  		if x&(1<<16) != 0 {
   822  			imm += ((1 << 8) - 1) << 40
   823  		}
   824  		if x&(1<<17) != 0 {
   825  			imm += ((1 << 8) - 1) << 48
   826  		}
   827  		if x&(1<<18) != 0 {
   828  			imm += ((1 << 8) - 1) << 56
   829  		}
   830  		return Imm64{imm, false}
   831  
   832  	case arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h:
   833  		pre := (x >> 5) & (1<<4 - 1)
   834  		exp := 1 - ((x >> 17) & 1)
   835  		exp = (exp << 2) + (((x >> 16) & 1) << 1) + ((x >> 9) & 1)
   836  		s := ((x >> 18) & 1)
   837  		return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)}
   838  
   839  	case arg_immediate_exp_3_pre_4_imm8:
   840  		pre := (x >> 13) & (1<<4 - 1)
   841  		exp := 1 - ((x >> 19) & 1)
   842  		exp = (exp << 2) + ((x >> 17) & (1<<2 - 1))
   843  		s := ((x >> 20) & 1)
   844  		return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)}
   845  
   846  	case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8:
   847  		fallthrough
   848  
   849  	case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8:
   850  		immh := (x >> 19) & (1<<4 - 1)
   851  		immb := (x >> 16) & (1<<3 - 1)
   852  		if (immh >> 2) == 1 {
   853  			return Imm{64 - ((immh << 3) + immb), true}
   854  		} else if (immh >> 3) == 1 {
   855  			return Imm{128 - ((immh << 3) + immb), true}
   856  		} else {
   857  			return nil
   858  		}
   859  
   860  	case arg_immediate_fbits_min_1_max_32_sub_64_scale:
   861  		scale := (x >> 10) & (1<<6 - 1)
   862  		fbits := 64 - scale
   863  		if fbits > 32 {
   864  			return nil
   865  		}
   866  		return Imm{fbits, true}
   867  
   868  	case arg_immediate_fbits_min_1_max_64_sub_64_scale:
   869  		scale := (x >> 10) & (1<<6 - 1)
   870  		fbits := 64 - scale
   871  		return Imm{fbits, true}
   872  
   873  	case arg_immediate_floatzero:
   874  		return Imm{0, true}
   875  
   876  	case arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10:
   877  		Q := (x >> 30) & 1
   878  		imm4 := (x >> 11) & (1<<4 - 1)
   879  		if Q == 1 || (imm4>>3) == 0 {
   880  			return Imm{imm4, true}
   881  		} else {
   882  			return nil
   883  		}
   884  
   885  	case arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1:
   886  		var shift uint8
   887  		imm8 := (x >> 16) & (1<<3 - 1)
   888  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   889  		if (x>>12)&1 == 0 {
   890  			shift = 8 + 128
   891  		} else {
   892  			shift = 16 + 128
   893  		}
   894  		return ImmShift{uint16(imm8), shift}
   895  
   896  	case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1:
   897  		imm8 := (x >> 16) & (1<<3 - 1)
   898  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   899  		cmode1 := (x >> 13) & 1
   900  		shift := 8 * cmode1
   901  		return ImmShift{uint16(imm8), uint8(shift)}
   902  
   903  	case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3:
   904  		imm8 := (x >> 16) & (1<<3 - 1)
   905  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   906  		cmode1 := (x >> 13) & (1<<2 - 1)
   907  		shift := 8 * cmode1
   908  		return ImmShift{uint16(imm8), uint8(shift)}
   909  
   910  	case arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h:
   911  		imm8 := (x >> 16) & (1<<3 - 1)
   912  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   913  		return ImmShift{uint16(imm8), 0}
   914  
   915  	case arg_immediate_zero:
   916  		return Imm{0, true}
   917  
   918  	case arg_Qd:
   919  		return Q0 + Reg(x&(1<<5-1))
   920  
   921  	case arg_Qn:
   922  		return Q0 + Reg((x>>5)&(1<<5-1))
   923  
   924  	case arg_Qt:
   925  		return Q0 + Reg(x&(1<<5-1))
   926  
   927  	case arg_Qt2:
   928  		return Q0 + Reg((x>>10)&(1<<5-1))
   929  
   930  	case arg_Rn_16_5__W_1__W_2__W_4__X_8:
   931  		imm5 := (x >> 16) & (1<<5 - 1)
   932  		if ((imm5 & 1) == 1) || ((imm5 & 2) == 2) || ((imm5 & 4) == 4) {
   933  			return W0 + Reg((x>>5)&(1<<5-1))
   934  		} else if (imm5 & 8) == 8 {
   935  			return X0 + Reg((x>>5)&(1<<5-1))
   936  		} else {
   937  			return nil
   938  		}
   939  
   940  	case arg_St:
   941  		return S0 + Reg(x&(1<<5-1))
   942  
   943  	case arg_St2:
   944  		return S0 + Reg((x>>10)&(1<<5-1))
   945  
   946  	case arg_Vd_16_5__B_1__H_2__S_4__D_8:
   947  		imm5 := (x >> 16) & (1<<5 - 1)
   948  		Rd := x & (1<<5 - 1)
   949  		if imm5&1 == 1 {
   950  			return B0 + Reg(Rd)
   951  		} else if imm5&2 == 2 {
   952  			return H0 + Reg(Rd)
   953  		} else if imm5&4 == 4 {
   954  			return S0 + Reg(Rd)
   955  		} else if imm5&8 == 8 {
   956  			return D0 + Reg(Rd)
   957  		} else {
   958  			return nil
   959  		}
   960  
   961  	case arg_Vd_19_4__B_1__H_2__S_4:
   962  		immh := (x >> 19) & (1<<4 - 1)
   963  		Rd := x & (1<<5 - 1)
   964  		if immh == 1 {
   965  			return B0 + Reg(Rd)
   966  		} else if immh>>1 == 1 {
   967  			return H0 + Reg(Rd)
   968  		} else if immh>>2 == 1 {
   969  			return S0 + Reg(Rd)
   970  		} else {
   971  			return nil
   972  		}
   973  
   974  	case arg_Vd_19_4__B_1__H_2__S_4__D_8:
   975  		immh := (x >> 19) & (1<<4 - 1)
   976  		Rd := x & (1<<5 - 1)
   977  		if immh == 1 {
   978  			return B0 + Reg(Rd)
   979  		} else if immh>>1 == 1 {
   980  			return H0 + Reg(Rd)
   981  		} else if immh>>2 == 1 {
   982  			return S0 + Reg(Rd)
   983  		} else if immh>>3 == 1 {
   984  			return D0 + Reg(Rd)
   985  		} else {
   986  			return nil
   987  		}
   988  
   989  	case arg_Vd_19_4__D_8:
   990  		immh := (x >> 19) & (1<<4 - 1)
   991  		Rd := x & (1<<5 - 1)
   992  		if immh>>3 == 1 {
   993  			return D0 + Reg(Rd)
   994  		} else {
   995  			return nil
   996  		}
   997  
   998  	case arg_Vd_19_4__S_4__D_8:
   999  		immh := (x >> 19) & (1<<4 - 1)
  1000  		Rd := x & (1<<5 - 1)
  1001  		if immh>>2 == 1 {
  1002  			return S0 + Reg(Rd)
  1003  		} else if immh>>3 == 1 {
  1004  			return D0 + Reg(Rd)
  1005  		} else {
  1006  			return nil
  1007  		}
  1008  
  1009  	case arg_Vd_22_1__S_0:
  1010  		sz := (x >> 22) & 1
  1011  		Rd := x & (1<<5 - 1)
  1012  		if sz == 0 {
  1013  			return S0 + Reg(Rd)
  1014  		} else {
  1015  			return nil
  1016  		}
  1017  
  1018  	case arg_Vd_22_1__S_0__D_1:
  1019  		sz := (x >> 22) & 1
  1020  		Rd := x & (1<<5 - 1)
  1021  		if sz == 0 {
  1022  			return S0 + Reg(Rd)
  1023  		} else {
  1024  			return D0 + Reg(Rd)
  1025  		}
  1026  
  1027  	case arg_Vd_22_1__S_1:
  1028  		sz := (x >> 22) & 1
  1029  		Rd := x & (1<<5 - 1)
  1030  		if sz == 1 {
  1031  			return S0 + Reg(Rd)
  1032  		} else {
  1033  			return nil
  1034  		}
  1035  
  1036  	case arg_Vd_22_2__B_0__H_1__S_2:
  1037  		size := (x >> 22) & (1<<2 - 1)
  1038  		Rd := x & (1<<5 - 1)
  1039  		if size == 0 {
  1040  			return B0 + Reg(Rd)
  1041  		} else if size == 1 {
  1042  			return H0 + Reg(Rd)
  1043  		} else if size == 2 {
  1044  			return S0 + Reg(Rd)
  1045  		} else {
  1046  			return nil
  1047  		}
  1048  
  1049  	case arg_Vd_22_2__B_0__H_1__S_2__D_3:
  1050  		size := (x >> 22) & (1<<2 - 1)
  1051  		Rd := x & (1<<5 - 1)
  1052  		if size == 0 {
  1053  			return B0 + Reg(Rd)
  1054  		} else if size == 1 {
  1055  			return H0 + Reg(Rd)
  1056  		} else if size == 2 {
  1057  			return S0 + Reg(Rd)
  1058  		} else {
  1059  			return D0 + Reg(Rd)
  1060  		}
  1061  
  1062  	case arg_Vd_22_2__D_3:
  1063  		size := (x >> 22) & (1<<2 - 1)
  1064  		Rd := x & (1<<5 - 1)
  1065  		if size == 3 {
  1066  			return D0 + Reg(Rd)
  1067  		} else {
  1068  			return nil
  1069  		}
  1070  
  1071  	case arg_Vd_22_2__H_0__S_1__D_2:
  1072  		size := (x >> 22) & (1<<2 - 1)
  1073  		Rd := x & (1<<5 - 1)
  1074  		if size == 0 {
  1075  			return H0 + Reg(Rd)
  1076  		} else if size == 1 {
  1077  			return S0 + Reg(Rd)
  1078  		} else if size == 2 {
  1079  			return D0 + Reg(Rd)
  1080  		} else {
  1081  			return nil
  1082  		}
  1083  
  1084  	case arg_Vd_22_2__H_1__S_2:
  1085  		size := (x >> 22) & (1<<2 - 1)
  1086  		Rd := x & (1<<5 - 1)
  1087  		if size == 1 {
  1088  			return H0 + Reg(Rd)
  1089  		} else if size == 2 {
  1090  			return S0 + Reg(Rd)
  1091  		} else {
  1092  			return nil
  1093  		}
  1094  
  1095  	case arg_Vd_22_2__S_1__D_2:
  1096  		size := (x >> 22) & (1<<2 - 1)
  1097  		Rd := x & (1<<5 - 1)
  1098  		if size == 1 {
  1099  			return S0 + Reg(Rd)
  1100  		} else if size == 2 {
  1101  			return D0 + Reg(Rd)
  1102  		} else {
  1103  			return nil
  1104  		}
  1105  
  1106  	case arg_Vd_arrangement_16B:
  1107  		Rd := x & (1<<5 - 1)
  1108  		return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1109  
  1110  	case arg_Vd_arrangement_2D:
  1111  		Rd := x & (1<<5 - 1)
  1112  		return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1113  
  1114  	case arg_Vd_arrangement_4S:
  1115  		Rd := x & (1<<5 - 1)
  1116  		return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1117  
  1118  	case arg_Vd_arrangement_D_index__1:
  1119  		Rd := x & (1<<5 - 1)
  1120  		return RegisterWithArrangementAndIndex{V0 + Reg(Rd), ArrangementD, 1, 0}
  1121  
  1122  	case arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1:
  1123  		var a Arrangement
  1124  		var index uint32
  1125  		Rd := x & (1<<5 - 1)
  1126  		imm5 := (x >> 16) & (1<<5 - 1)
  1127  		if imm5&1 == 1 {
  1128  			a = ArrangementB
  1129  			index = imm5 >> 1
  1130  		} else if imm5&2 == 2 {
  1131  			a = ArrangementH
  1132  			index = imm5 >> 2
  1133  		} else if imm5&4 == 4 {
  1134  			a = ArrangementS
  1135  			index = imm5 >> 3
  1136  		} else if imm5&8 == 8 {
  1137  			a = ArrangementD
  1138  			index = imm5 >> 4
  1139  		} else {
  1140  			return nil
  1141  		}
  1142  		return RegisterWithArrangementAndIndex{V0 + Reg(Rd), a, uint8(index), 0}
  1143  
  1144  	case arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
  1145  		Rd := x & (1<<5 - 1)
  1146  		imm5 := (x >> 16) & (1<<5 - 1)
  1147  		Q := (x >> 30) & 1
  1148  		if imm5&1 == 1 {
  1149  			if Q == 0 {
  1150  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1151  			} else {
  1152  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1153  			}
  1154  		} else if imm5&2 == 2 {
  1155  			if Q == 0 {
  1156  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1157  			} else {
  1158  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1159  			}
  1160  		} else if imm5&4 == 4 {
  1161  			if Q == 0 {
  1162  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1163  			} else {
  1164  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1165  			}
  1166  		} else if (imm5&8 == 8) && (Q == 1) {
  1167  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1168  		} else {
  1169  			return nil
  1170  		}
  1171  
  1172  	case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81:
  1173  		Rd := x & (1<<5 - 1)
  1174  		immh := (x >> 19) & (1<<4 - 1)
  1175  		Q := (x >> 30) & 1
  1176  		if immh>>2 == 1 {
  1177  			if Q == 0 {
  1178  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1179  			} else {
  1180  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1181  			}
  1182  		} else if immh>>3 == 1 {
  1183  			if Q == 1 {
  1184  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1185  			}
  1186  		}
  1187  		return nil
  1188  
  1189  	case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41:
  1190  		Rd := x & (1<<5 - 1)
  1191  		immh := (x >> 19) & (1<<4 - 1)
  1192  		Q := (x >> 30) & 1
  1193  		if immh == 1 {
  1194  			if Q == 0 {
  1195  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1196  			} else {
  1197  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1198  			}
  1199  		} else if immh>>1 == 1 {
  1200  			if Q == 0 {
  1201  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1202  			} else {
  1203  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1204  			}
  1205  		} else if immh>>2 == 1 {
  1206  			if Q == 0 {
  1207  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1208  			} else {
  1209  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1210  			}
  1211  		}
  1212  		return nil
  1213  
  1214  	case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
  1215  		Rd := x & (1<<5 - 1)
  1216  		immh := (x >> 19) & (1<<4 - 1)
  1217  		Q := (x >> 30) & 1
  1218  		if immh == 1 {
  1219  			if Q == 0 {
  1220  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1221  			} else {
  1222  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1223  			}
  1224  		} else if immh>>1 == 1 {
  1225  			if Q == 0 {
  1226  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1227  			} else {
  1228  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1229  			}
  1230  		} else if immh>>2 == 1 {
  1231  			if Q == 0 {
  1232  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1233  			} else {
  1234  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1235  			}
  1236  		} else if immh>>3 == 1 {
  1237  			if Q == 1 {
  1238  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1239  			}
  1240  		}
  1241  		return nil
  1242  
  1243  	case arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4:
  1244  		Rd := x & (1<<5 - 1)
  1245  		immh := (x >> 19) & (1<<4 - 1)
  1246  		if immh == 1 {
  1247  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1248  		} else if immh>>1 == 1 {
  1249  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1250  		} else if immh>>2 == 1 {
  1251  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1252  		}
  1253  		return nil
  1254  
  1255  	case arg_Vd_arrangement_Q___2S_0__4S_1:
  1256  		Rd := x & (1<<5 - 1)
  1257  		Q := (x >> 30) & 1
  1258  		if Q == 0 {
  1259  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1260  		} else {
  1261  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1262  		}
  1263  
  1264  	case arg_Vd_arrangement_Q___4H_0__8H_1:
  1265  		Rd := x & (1<<5 - 1)
  1266  		Q := (x >> 30) & 1
  1267  		if Q == 0 {
  1268  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1269  		} else {
  1270  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1271  		}
  1272  
  1273  	case arg_Vd_arrangement_Q___8B_0__16B_1:
  1274  		Rd := x & (1<<5 - 1)
  1275  		Q := (x >> 30) & 1
  1276  		if Q == 0 {
  1277  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1278  		} else {
  1279  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1280  		}
  1281  
  1282  	case arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11:
  1283  		Rd := x & (1<<5 - 1)
  1284  		Q := (x >> 30) & 1
  1285  		sz := (x >> 22) & 1
  1286  		if sz == 0 && Q == 0 {
  1287  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1288  		} else if sz == 0 && Q == 1 {
  1289  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1290  		} else if sz == 1 && Q == 1 {
  1291  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1292  		}
  1293  		return nil
  1294  
  1295  	case arg_Vd_arrangement_size___4S_1__2D_2:
  1296  		Rd := x & (1<<5 - 1)
  1297  		size := (x >> 22) & 3
  1298  		if size == 1 {
  1299  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1300  		} else if size == 2 {
  1301  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1302  		}
  1303  		return nil
  1304  
  1305  	case arg_Vd_arrangement_size___8H_0__1Q_3:
  1306  		Rd := x & (1<<5 - 1)
  1307  		size := (x >> 22) & 3
  1308  		if size == 0 {
  1309  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1310  		} else if size == 3 {
  1311  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1Q, 0}
  1312  		}
  1313  		return nil
  1314  
  1315  	case arg_Vd_arrangement_size___8H_0__4S_1__2D_2:
  1316  		Rd := x & (1<<5 - 1)
  1317  		size := (x >> 22) & 3
  1318  		if size == 0 {
  1319  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1320  		} else if size == 1 {
  1321  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1322  		} else if size == 2 {
  1323  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1324  		}
  1325  		return nil
  1326  
  1327  	case arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21:
  1328  		Rd := x & (1<<5 - 1)
  1329  		size := (x >> 22) & 3
  1330  		Q := (x >> 30) & 1
  1331  		if size == 0 && Q == 0 {
  1332  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1333  		} else if size == 0 && Q == 1 {
  1334  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1335  		} else if size == 1 && Q == 0 {
  1336  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1337  		} else if size == 1 && Q == 1 {
  1338  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1339  		} else if size == 2 && Q == 0 {
  1340  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1D, 0}
  1341  		} else if size == 2 && Q == 1 {
  1342  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1343  		}
  1344  		return nil
  1345  
  1346  	case arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
  1347  		Rd := x & (1<<5 - 1)
  1348  		size := (x >> 22) & 3
  1349  		Q := (x >> 30) & 1
  1350  		if size == 1 && Q == 0 {
  1351  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1352  		} else if size == 1 && Q == 1 {
  1353  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1354  		} else if size == 2 && Q == 0 {
  1355  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1356  		} else if size == 2 && Q == 1 {
  1357  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1358  		}
  1359  		return nil
  1360  
  1361  	case arg_Vd_arrangement_size_Q___8B_00__16B_01:
  1362  		Rd := x & (1<<5 - 1)
  1363  		size := (x >> 22) & 3
  1364  		Q := (x >> 30) & 1
  1365  		if size == 0 && Q == 0 {
  1366  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1367  		} else if size == 0 && Q == 1 {
  1368  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1369  		}
  1370  		return nil
  1371  
  1372  	case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11:
  1373  		Rd := x & (1<<5 - 1)
  1374  		size := (x >> 22) & 3
  1375  		Q := (x >> 30) & 1
  1376  		if size == 0 && Q == 0 {
  1377  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1378  		} else if size == 0 && Q == 1 {
  1379  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1380  		} else if size == 1 && Q == 0 {
  1381  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1382  		} else if size == 1 && Q == 1 {
  1383  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1384  		}
  1385  		return nil
  1386  
  1387  	case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
  1388  		Rd := x & (1<<5 - 1)
  1389  		size := (x >> 22) & 3
  1390  		Q := (x >> 30) & 1
  1391  		if size == 0 && Q == 0 {
  1392  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1393  		} else if size == 0 && Q == 1 {
  1394  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1395  		} else if size == 1 && Q == 0 {
  1396  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1397  		} else if size == 1 && Q == 1 {
  1398  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1399  		} else if size == 2 && Q == 0 {
  1400  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1401  		} else if size == 2 && Q == 1 {
  1402  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1403  		}
  1404  		return nil
  1405  
  1406  	case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  1407  		Rd := x & (1<<5 - 1)
  1408  		size := (x >> 22) & 3
  1409  		Q := (x >> 30) & 1
  1410  		if size == 0 && Q == 0 {
  1411  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1412  		} else if size == 0 && Q == 1 {
  1413  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1414  		} else if size == 1 && Q == 0 {
  1415  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1416  		} else if size == 1 && Q == 1 {
  1417  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1418  		} else if size == 2 && Q == 0 {
  1419  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1420  		} else if size == 2 && Q == 1 {
  1421  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1422  		} else if size == 3 && Q == 1 {
  1423  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1424  		}
  1425  		return nil
  1426  
  1427  	case arg_Vd_arrangement_sz___4S_0__2D_1:
  1428  		Rd := x & (1<<5 - 1)
  1429  		sz := (x >> 22) & 1
  1430  		if sz == 0 {
  1431  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1432  		} else {
  1433  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1434  		}
  1435  
  1436  	case arg_Vd_arrangement_sz_Q___2S_00__4S_01:
  1437  		Rd := x & (1<<5 - 1)
  1438  		sz := (x >> 22) & 1
  1439  		Q := (x >> 30) & 1
  1440  		if sz == 0 && Q == 0 {
  1441  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1442  		} else if sz == 0 && Q == 1 {
  1443  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1444  		}
  1445  		return nil
  1446  
  1447  	case arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11:
  1448  		Rd := x & (1<<5 - 1)
  1449  		sz := (x >> 22) & 1
  1450  		Q := (x >> 30) & 1
  1451  		if sz == 0 && Q == 0 {
  1452  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1453  		} else if sz == 0 && Q == 1 {
  1454  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1455  		} else if sz == 1 && Q == 1 {
  1456  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1457  		}
  1458  		return nil
  1459  
  1460  	case arg_Vd_arrangement_sz_Q___2S_10__4S_11:
  1461  		Rd := x & (1<<5 - 1)
  1462  		sz := (x >> 22) & 1
  1463  		Q := (x >> 30) & 1
  1464  		if sz == 1 && Q == 0 {
  1465  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1466  		} else if sz == 1 && Q == 1 {
  1467  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1468  		}
  1469  		return nil
  1470  
  1471  	case arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11:
  1472  		Rd := x & (1<<5 - 1)
  1473  		sz := (x >> 22) & 1
  1474  		Q := (x >> 30) & 1
  1475  		if sz == 0 && Q == 0 {
  1476  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1477  		} else if sz == 0 && Q == 1 {
  1478  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1479  		} else if sz == 1 && Q == 0 {
  1480  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1481  		} else /* sz == 1 && Q == 1 */ {
  1482  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1483  		}
  1484  
  1485  	case arg_Vm_22_1__S_0__D_1:
  1486  		sz := (x >> 22) & 1
  1487  		Rm := (x >> 16) & (1<<5 - 1)
  1488  		if sz == 0 {
  1489  			return S0 + Reg(Rm)
  1490  		} else {
  1491  			return D0 + Reg(Rm)
  1492  		}
  1493  
  1494  	case arg_Vm_22_2__B_0__H_1__S_2__D_3:
  1495  		size := (x >> 22) & (1<<2 - 1)
  1496  		Rm := (x >> 16) & (1<<5 - 1)
  1497  		if size == 0 {
  1498  			return B0 + Reg(Rm)
  1499  		} else if size == 1 {
  1500  			return H0 + Reg(Rm)
  1501  		} else if size == 2 {
  1502  			return S0 + Reg(Rm)
  1503  		} else {
  1504  			return D0 + Reg(Rm)
  1505  		}
  1506  
  1507  	case arg_Vm_22_2__D_3:
  1508  		size := (x >> 22) & (1<<2 - 1)
  1509  		Rm := (x >> 16) & (1<<5 - 1)
  1510  		if size == 3 {
  1511  			return D0 + Reg(Rm)
  1512  		} else {
  1513  			return nil
  1514  		}
  1515  
  1516  	case arg_Vm_22_2__H_1__S_2:
  1517  		size := (x >> 22) & (1<<2 - 1)
  1518  		Rm := (x >> 16) & (1<<5 - 1)
  1519  		if size == 1 {
  1520  			return H0 + Reg(Rm)
  1521  		} else if size == 2 {
  1522  			return S0 + Reg(Rm)
  1523  		} else {
  1524  			return nil
  1525  		}
  1526  
  1527  	case arg_Vm_arrangement_4S:
  1528  		Rm := (x >> 16) & (1<<5 - 1)
  1529  		return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1530  
  1531  	case arg_Vm_arrangement_Q___8B_0__16B_1:
  1532  		Rm := (x >> 16) & (1<<5 - 1)
  1533  		Q := (x >> 30) & 1
  1534  		if Q == 0 {
  1535  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1536  		} else {
  1537  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1538  		}
  1539  
  1540  	case arg_Vm_arrangement_size___8H_0__4S_1__2D_2:
  1541  		Rm := (x >> 16) & (1<<5 - 1)
  1542  		size := (x >> 22) & 3
  1543  		if size == 0 {
  1544  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1545  		} else if size == 1 {
  1546  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1547  		} else if size == 2 {
  1548  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1549  		}
  1550  		return nil
  1551  
  1552  	case arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1:
  1553  		var a Arrangement
  1554  		var index uint32
  1555  		var vm uint32
  1556  		Rm := (x >> 16) & (1<<4 - 1)
  1557  		size := (x >> 22) & 3
  1558  		H := (x >> 11) & 1
  1559  		L := (x >> 21) & 1
  1560  		M := (x >> 20) & 1
  1561  		if size == 1 {
  1562  			a = ArrangementH
  1563  			index = (H << 2) | (L << 1) | M
  1564  			vm = Rm
  1565  		} else if size == 2 {
  1566  			a = ArrangementS
  1567  			index = (H << 1) | L
  1568  			vm = (M << 4) | Rm
  1569  		} else {
  1570  			return nil
  1571  		}
  1572  		return RegisterWithArrangementAndIndex{V0 + Reg(vm), a, uint8(index), 0}
  1573  
  1574  	case arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
  1575  		Rm := (x >> 16) & (1<<5 - 1)
  1576  		size := (x >> 22) & 3
  1577  		Q := (x >> 30) & 1
  1578  		if size == 1 && Q == 0 {
  1579  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
  1580  		} else if size == 1 && Q == 1 {
  1581  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1582  		} else if size == 2 && Q == 0 {
  1583  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1584  		} else if size == 2 && Q == 1 {
  1585  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1586  		}
  1587  		return nil
  1588  
  1589  	case arg_Vm_arrangement_size_Q___8B_00__16B_01:
  1590  		Rm := (x >> 16) & (1<<5 - 1)
  1591  		size := (x >> 22) & 3
  1592  		Q := (x >> 30) & 1
  1593  		if size == 0 && Q == 0 {
  1594  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1595  		} else if size == 0 && Q == 1 {
  1596  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1597  		}
  1598  		return nil
  1599  
  1600  	case arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31:
  1601  		Rm := (x >> 16) & (1<<5 - 1)
  1602  		size := (x >> 22) & 3
  1603  		Q := (x >> 30) & 1
  1604  		if size == 0 && Q == 0 {
  1605  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1606  		} else if size == 0 && Q == 1 {
  1607  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1608  		} else if size == 3 && Q == 0 {
  1609  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement1D, 0}
  1610  		} else if size == 3 && Q == 1 {
  1611  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1612  		}
  1613  		return nil
  1614  
  1615  	case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
  1616  		Rm := (x >> 16) & (1<<5 - 1)
  1617  		size := (x >> 22) & 3
  1618  		Q := (x >> 30) & 1
  1619  		if size == 0 && Q == 0 {
  1620  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1621  		} else if size == 0 && Q == 1 {
  1622  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1623  		} else if size == 1 && Q == 0 {
  1624  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
  1625  		} else if size == 1 && Q == 1 {
  1626  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1627  		} else if size == 2 && Q == 0 {
  1628  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1629  		} else if size == 2 && Q == 1 {
  1630  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1631  		}
  1632  		return nil
  1633  
  1634  	case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  1635  		Rm := (x >> 16) & (1<<5 - 1)
  1636  		size := (x >> 22) & 3
  1637  		Q := (x >> 30) & 1
  1638  		if size == 0 && Q == 0 {
  1639  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1640  		} else if size == 0 && Q == 1 {
  1641  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1642  		} else if size == 1 && Q == 0 {
  1643  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
  1644  		} else if size == 1 && Q == 1 {
  1645  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1646  		} else if size == 2 && Q == 0 {
  1647  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1648  		} else if size == 2 && Q == 1 {
  1649  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1650  		} else if size == 3 && Q == 1 {
  1651  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1652  		}
  1653  		return nil
  1654  
  1655  	case arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11:
  1656  		Rm := (x >> 16) & (1<<5 - 1)
  1657  		sz := (x >> 22) & 1
  1658  		Q := (x >> 30) & 1
  1659  		if sz == 0 && Q == 0 {
  1660  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1661  		} else if sz == 0 && Q == 1 {
  1662  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1663  		} else if sz == 1 && Q == 1 {
  1664  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1665  		}
  1666  		return nil
  1667  
  1668  	case arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1:
  1669  		var a Arrangement
  1670  		var index uint32
  1671  		Rm := (x >> 16) & (1<<5 - 1)
  1672  		sz := (x >> 22) & 1
  1673  		H := (x >> 11) & 1
  1674  		L := (x >> 21) & 1
  1675  		if sz == 0 {
  1676  			a = ArrangementS
  1677  			index = (H << 1) | L
  1678  		} else if sz == 1 && L == 0 {
  1679  			a = ArrangementD
  1680  			index = H
  1681  		} else {
  1682  			return nil
  1683  		}
  1684  		return RegisterWithArrangementAndIndex{V0 + Reg(Rm), a, uint8(index), 0}
  1685  
  1686  	case arg_Vn_19_4__B_1__H_2__S_4__D_8:
  1687  		immh := (x >> 19) & (1<<4 - 1)
  1688  		Rn := (x >> 5) & (1<<5 - 1)
  1689  		if immh == 1 {
  1690  			return B0 + Reg(Rn)
  1691  		} else if immh>>1 == 1 {
  1692  			return H0 + Reg(Rn)
  1693  		} else if immh>>2 == 1 {
  1694  			return S0 + Reg(Rn)
  1695  		} else if immh>>3 == 1 {
  1696  			return D0 + Reg(Rn)
  1697  		} else {
  1698  			return nil
  1699  		}
  1700  
  1701  	case arg_Vn_19_4__D_8:
  1702  		immh := (x >> 19) & (1<<4 - 1)
  1703  		Rn := (x >> 5) & (1<<5 - 1)
  1704  		if immh>>3 == 1 {
  1705  			return D0 + Reg(Rn)
  1706  		} else {
  1707  			return nil
  1708  		}
  1709  
  1710  	case arg_Vn_19_4__H_1__S_2__D_4:
  1711  		immh := (x >> 19) & (1<<4 - 1)
  1712  		Rn := (x >> 5) & (1<<5 - 1)
  1713  		if immh == 1 {
  1714  			return H0 + Reg(Rn)
  1715  		} else if immh>>1 == 1 {
  1716  			return S0 + Reg(Rn)
  1717  		} else if immh>>2 == 1 {
  1718  			return D0 + Reg(Rn)
  1719  		} else {
  1720  			return nil
  1721  		}
  1722  
  1723  	case arg_Vn_19_4__S_4__D_8:
  1724  		immh := (x >> 19) & (1<<4 - 1)
  1725  		Rn := (x >> 5) & (1<<5 - 1)
  1726  		if immh>>2 == 1 {
  1727  			return S0 + Reg(Rn)
  1728  		} else if immh>>3 == 1 {
  1729  			return D0 + Reg(Rn)
  1730  		} else {
  1731  			return nil
  1732  		}
  1733  
  1734  	case arg_Vn_1_arrangement_16B:
  1735  		Rn := (x >> 5) & (1<<5 - 1)
  1736  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 1}
  1737  
  1738  	case arg_Vn_22_1__D_1:
  1739  		sz := (x >> 22) & 1
  1740  		Rn := (x >> 5) & (1<<5 - 1)
  1741  		if sz == 1 {
  1742  			return D0 + Reg(Rn)
  1743  		}
  1744  		return nil
  1745  
  1746  	case arg_Vn_22_1__S_0__D_1:
  1747  		sz := (x >> 22) & 1
  1748  		Rn := (x >> 5) & (1<<5 - 1)
  1749  		if sz == 0 {
  1750  			return S0 + Reg(Rn)
  1751  		} else {
  1752  			return D0 + Reg(Rn)
  1753  		}
  1754  
  1755  	case arg_Vn_22_2__B_0__H_1__S_2__D_3:
  1756  		size := (x >> 22) & (1<<2 - 1)
  1757  		Rn := (x >> 5) & (1<<5 - 1)
  1758  		if size == 0 {
  1759  			return B0 + Reg(Rn)
  1760  		} else if size == 1 {
  1761  			return H0 + Reg(Rn)
  1762  		} else if size == 2 {
  1763  			return S0 + Reg(Rn)
  1764  		} else {
  1765  			return D0 + Reg(Rn)
  1766  		}
  1767  
  1768  	case arg_Vn_22_2__D_3:
  1769  		size := (x >> 22) & (1<<2 - 1)
  1770  		Rn := (x >> 5) & (1<<5 - 1)
  1771  		if size == 3 {
  1772  			return D0 + Reg(Rn)
  1773  		} else {
  1774  			return nil
  1775  		}
  1776  
  1777  	case arg_Vn_22_2__H_0__S_1__D_2:
  1778  		size := (x >> 22) & (1<<2 - 1)
  1779  		Rn := (x >> 5) & (1<<5 - 1)
  1780  		if size == 0 {
  1781  			return H0 + Reg(Rn)
  1782  		} else if size == 1 {
  1783  			return S0 + Reg(Rn)
  1784  		} else if size == 2 {
  1785  			return D0 + Reg(Rn)
  1786  		} else {
  1787  			return nil
  1788  		}
  1789  
  1790  	case arg_Vn_22_2__H_1__S_2:
  1791  		size := (x >> 22) & (1<<2 - 1)
  1792  		Rn := (x >> 5) & (1<<5 - 1)
  1793  		if size == 1 {
  1794  			return H0 + Reg(Rn)
  1795  		} else if size == 2 {
  1796  			return S0 + Reg(Rn)
  1797  		} else {
  1798  			return nil
  1799  		}
  1800  
  1801  	case arg_Vn_2_arrangement_16B:
  1802  		Rn := (x >> 5) & (1<<5 - 1)
  1803  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 2}
  1804  
  1805  	case arg_Vn_3_arrangement_16B:
  1806  		Rn := (x >> 5) & (1<<5 - 1)
  1807  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 3}
  1808  
  1809  	case arg_Vn_4_arrangement_16B:
  1810  		Rn := (x >> 5) & (1<<5 - 1)
  1811  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 4}
  1812  
  1813  	case arg_Vn_arrangement_16B:
  1814  		Rn := (x >> 5) & (1<<5 - 1)
  1815  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  1816  
  1817  	case arg_Vn_arrangement_4S:
  1818  		Rn := (x >> 5) & (1<<5 - 1)
  1819  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1820  
  1821  	case arg_Vn_arrangement_D_index__1:
  1822  		Rn := (x >> 5) & (1<<5 - 1)
  1823  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, 1, 0}
  1824  
  1825  	case arg_Vn_arrangement_D_index__imm5_1:
  1826  		Rn := (x >> 5) & (1<<5 - 1)
  1827  		index := (x >> 20) & 1
  1828  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, uint8(index), 0}
  1829  
  1830  	case arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1:
  1831  		var a Arrangement
  1832  		var index uint32
  1833  		Rn := (x >> 5) & (1<<5 - 1)
  1834  		imm5 := (x >> 16) & (1<<5 - 1)
  1835  		if imm5&1 == 1 {
  1836  			a = ArrangementB
  1837  			index = imm5 >> 1
  1838  		} else if imm5&2 == 2 {
  1839  			a = ArrangementH
  1840  			index = imm5 >> 2
  1841  		} else {
  1842  			return nil
  1843  		}
  1844  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1845  
  1846  	case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1:
  1847  		var a Arrangement
  1848  		var index uint32
  1849  		Rn := (x >> 5) & (1<<5 - 1)
  1850  		imm5 := (x >> 16) & (1<<5 - 1)
  1851  		imm4 := (x >> 11) & (1<<4 - 1)
  1852  		if imm5&1 == 1 {
  1853  			a = ArrangementB
  1854  			index = imm4
  1855  		} else if imm5&2 == 2 {
  1856  			a = ArrangementH
  1857  			index = imm4 >> 1
  1858  		} else if imm5&4 == 4 {
  1859  			a = ArrangementS
  1860  			index = imm4 >> 2
  1861  		} else if imm5&8 == 8 {
  1862  			a = ArrangementD
  1863  			index = imm4 >> 3
  1864  		} else {
  1865  			return nil
  1866  		}
  1867  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1868  
  1869  	case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1:
  1870  		var a Arrangement
  1871  		var index uint32
  1872  		Rn := (x >> 5) & (1<<5 - 1)
  1873  		imm5 := (x >> 16) & (1<<5 - 1)
  1874  		if imm5&1 == 1 {
  1875  			a = ArrangementB
  1876  			index = imm5 >> 1
  1877  		} else if imm5&2 == 2 {
  1878  			a = ArrangementH
  1879  			index = imm5 >> 2
  1880  		} else if imm5&4 == 4 {
  1881  			a = ArrangementS
  1882  			index = imm5 >> 3
  1883  		} else if imm5&8 == 8 {
  1884  			a = ArrangementD
  1885  			index = imm5 >> 4
  1886  		} else {
  1887  			return nil
  1888  		}
  1889  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1890  
  1891  	case arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1:
  1892  		var a Arrangement
  1893  		var index uint32
  1894  		Rn := (x >> 5) & (1<<5 - 1)
  1895  		imm5 := (x >> 16) & (1<<5 - 1)
  1896  		if imm5&1 == 1 {
  1897  			a = ArrangementB
  1898  			index = imm5 >> 1
  1899  		} else if imm5&2 == 2 {
  1900  			a = ArrangementH
  1901  			index = imm5 >> 2
  1902  		} else if imm5&4 == 4 {
  1903  			a = ArrangementS
  1904  			index = imm5 >> 3
  1905  		} else {
  1906  			return nil
  1907  		}
  1908  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1909  
  1910  	case arg_Vn_arrangement_imm5___D_8_index__imm5_1:
  1911  		var a Arrangement
  1912  		var index uint32
  1913  		Rn := (x >> 5) & (1<<5 - 1)
  1914  		imm5 := (x >> 16) & (1<<5 - 1)
  1915  		if imm5&15 == 8 {
  1916  			a = ArrangementD
  1917  			index = imm5 >> 4
  1918  		} else {
  1919  			return nil
  1920  		}
  1921  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1922  
  1923  	case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81:
  1924  		Rn := (x >> 5) & (1<<5 - 1)
  1925  		immh := (x >> 19) & (1<<4 - 1)
  1926  		Q := (x >> 30) & 1
  1927  		if immh>>2 == 1 {
  1928  			if Q == 0 {
  1929  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  1930  			} else {
  1931  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1932  			}
  1933  		} else if immh>>3 == 1 {
  1934  			if Q == 1 {
  1935  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  1936  			}
  1937  		}
  1938  		return nil
  1939  
  1940  	case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41:
  1941  		Rn := (x >> 5) & (1<<5 - 1)
  1942  		immh := (x >> 19) & (1<<4 - 1)
  1943  		Q := (x >> 30) & 1
  1944  		if immh == 1 {
  1945  			if Q == 0 {
  1946  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  1947  			} else {
  1948  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  1949  			}
  1950  		} else if immh>>1 == 1 {
  1951  			if Q == 0 {
  1952  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  1953  			} else {
  1954  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  1955  			}
  1956  		} else if immh>>2 == 1 {
  1957  			if Q == 0 {
  1958  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  1959  			} else {
  1960  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1961  			}
  1962  		}
  1963  		return nil
  1964  
  1965  	case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
  1966  		Rn := (x >> 5) & (1<<5 - 1)
  1967  		immh := (x >> 19) & (1<<4 - 1)
  1968  		Q := (x >> 30) & 1
  1969  		if immh == 1 {
  1970  			if Q == 0 {
  1971  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  1972  			} else {
  1973  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  1974  			}
  1975  		} else if immh>>1 == 1 {
  1976  			if Q == 0 {
  1977  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  1978  			} else {
  1979  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  1980  			}
  1981  		} else if immh>>2 == 1 {
  1982  			if Q == 0 {
  1983  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  1984  			} else {
  1985  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1986  			}
  1987  		} else if immh>>3 == 1 {
  1988  			if Q == 1 {
  1989  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  1990  			}
  1991  		}
  1992  		return nil
  1993  
  1994  	case arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4:
  1995  		Rn := (x >> 5) & (1<<5 - 1)
  1996  		immh := (x >> 19) & (1<<4 - 1)
  1997  		if immh == 1 {
  1998  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  1999  		} else if immh>>1 == 1 {
  2000  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2001  		} else if immh>>2 == 1 {
  2002  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2003  		}
  2004  		return nil
  2005  
  2006  	case arg_Vn_arrangement_Q___8B_0__16B_1:
  2007  		Rn := (x >> 5) & (1<<5 - 1)
  2008  		Q := (x >> 30) & 1
  2009  		if Q == 0 {
  2010  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2011  		} else {
  2012  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2013  		}
  2014  
  2015  	case arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11:
  2016  		Rn := (x >> 5) & (1<<5 - 1)
  2017  		Q := (x >> 30) & 1
  2018  		sz := (x >> 22) & 1
  2019  		if sz == 0 && Q == 0 {
  2020  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2021  		} else if sz == 0 && Q == 1 {
  2022  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2023  		} else if sz == 1 && Q == 1 {
  2024  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2025  		}
  2026  		return nil
  2027  
  2028  	case arg_Vn_arrangement_Q_sz___4S_10:
  2029  		Rn := (x >> 5) & (1<<5 - 1)
  2030  		Q := (x >> 30) & 1
  2031  		sz := (x >> 22) & 1
  2032  		if sz == 0 && Q == 1 {
  2033  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2034  		}
  2035  		return nil
  2036  
  2037  	case arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1:
  2038  		var index uint32
  2039  		Rn := (x >> 5) & (1<<5 - 1)
  2040  		imm5 := (x >> 16) & (1<<5 - 1)
  2041  		index = imm5 >> 3
  2042  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementS, uint8(index), 0}
  2043  
  2044  	case arg_Vn_arrangement_size___2D_3:
  2045  		Rn := (x >> 5) & (1<<5 - 1)
  2046  		size := (x >> 22) & 3
  2047  		if size == 3 {
  2048  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2049  		}
  2050  		return nil
  2051  
  2052  	case arg_Vn_arrangement_size___8H_0__4S_1__2D_2:
  2053  		Rn := (x >> 5) & (1<<5 - 1)
  2054  		size := (x >> 22) & 3
  2055  		if size == 0 {
  2056  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2057  		} else if size == 1 {
  2058  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2059  		} else if size == 2 {
  2060  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2061  		}
  2062  		return nil
  2063  
  2064  	case arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
  2065  		Rn := (x >> 5) & (1<<5 - 1)
  2066  		size := (x >> 22) & 3
  2067  		Q := (x >> 30) & 1
  2068  		if size == 1 && Q == 0 {
  2069  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2070  		} else if size == 1 && Q == 1 {
  2071  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2072  		} else if size == 2 && Q == 0 {
  2073  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2074  		} else if size == 2 && Q == 1 {
  2075  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2076  		}
  2077  		return nil
  2078  
  2079  	case arg_Vn_arrangement_size_Q___8B_00__16B_01:
  2080  		Rn := (x >> 5) & (1<<5 - 1)
  2081  		size := (x >> 22) & 3
  2082  		Q := (x >> 30) & 1
  2083  		if size == 0 && Q == 0 {
  2084  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2085  		} else if size == 0 && Q == 1 {
  2086  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2087  		}
  2088  		return nil
  2089  
  2090  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31:
  2091  		Rn := (x >> 5) & (1<<5 - 1)
  2092  		size := (x >> 22) & 3
  2093  		Q := (x >> 30) & 1
  2094  		if size == 0 && Q == 0 {
  2095  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2096  		} else if size == 0 && Q == 1 {
  2097  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2098  		} else if size == 3 && Q == 0 {
  2099  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement1D, 0}
  2100  		} else if size == 3 && Q == 1 {
  2101  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2102  		}
  2103  		return nil
  2104  
  2105  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11:
  2106  		Rn := (x >> 5) & (1<<5 - 1)
  2107  		size := (x >> 22) & 3
  2108  		Q := (x >> 30) & 1
  2109  		if size == 0 && Q == 0 {
  2110  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2111  		} else if size == 0 && Q == 1 {
  2112  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2113  		} else if size == 1 && Q == 0 {
  2114  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2115  		} else if size == 1 && Q == 1 {
  2116  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2117  		}
  2118  		return nil
  2119  
  2120  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
  2121  		Rn := (x >> 5) & (1<<5 - 1)
  2122  		size := (x >> 22) & 3
  2123  		Q := (x >> 30) & 1
  2124  		if size == 0 && Q == 0 {
  2125  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2126  		} else if size == 0 && Q == 1 {
  2127  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2128  		} else if size == 1 && Q == 0 {
  2129  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2130  		} else if size == 1 && Q == 1 {
  2131  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2132  		} else if size == 2 && Q == 0 {
  2133  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2134  		} else if size == 2 && Q == 1 {
  2135  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2136  		}
  2137  		return nil
  2138  
  2139  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2140  		Rn := (x >> 5) & (1<<5 - 1)
  2141  		size := (x >> 22) & 3
  2142  		Q := (x >> 30) & 1
  2143  		if size == 0 && Q == 0 {
  2144  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2145  		} else if size == 0 && Q == 1 {
  2146  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2147  		} else if size == 1 && Q == 0 {
  2148  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2149  		} else if size == 1 && Q == 1 {
  2150  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2151  		} else if size == 2 && Q == 0 {
  2152  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2153  		} else if size == 2 && Q == 1 {
  2154  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2155  		} else if size == 3 && Q == 1 {
  2156  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2157  		}
  2158  		return nil
  2159  
  2160  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21:
  2161  		Rn := (x >> 5) & (1<<5 - 1)
  2162  		size := (x >> 22) & 3
  2163  		Q := (x >> 30) & 1
  2164  		if size == 0 && Q == 0 {
  2165  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2166  		} else if size == 0 && Q == 1 {
  2167  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2168  		} else if size == 1 && Q == 0 {
  2169  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2170  		} else if size == 1 && Q == 1 {
  2171  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2172  		} else if size == 2 && Q == 1 {
  2173  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2174  		}
  2175  		return nil
  2176  
  2177  	case arg_Vn_arrangement_sz___2D_1:
  2178  		Rn := (x >> 5) & (1<<5 - 1)
  2179  		sz := (x >> 22) & 1
  2180  		if sz == 1 {
  2181  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2182  		}
  2183  		return nil
  2184  
  2185  	case arg_Vn_arrangement_sz___2S_0__2D_1:
  2186  		Rn := (x >> 5) & (1<<5 - 1)
  2187  		sz := (x >> 22) & 1
  2188  		if sz == 0 {
  2189  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2190  		} else {
  2191  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2192  		}
  2193  
  2194  	case arg_Vn_arrangement_sz___4S_0__2D_1:
  2195  		Rn := (x >> 5) & (1<<5 - 1)
  2196  		sz := (x >> 22) & 1
  2197  		if sz == 0 {
  2198  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2199  		} else {
  2200  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2201  		}
  2202  
  2203  	case arg_Vn_arrangement_sz_Q___2S_00__4S_01:
  2204  		Rn := (x >> 5) & (1<<5 - 1)
  2205  		sz := (x >> 22) & 1
  2206  		Q := (x >> 30) & 1
  2207  		if sz == 0 && Q == 0 {
  2208  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2209  		} else if sz == 0 && Q == 1 {
  2210  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2211  		}
  2212  		return nil
  2213  
  2214  	case arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11:
  2215  		Rn := (x >> 5) & (1<<5 - 1)
  2216  		sz := (x >> 22) & 1
  2217  		Q := (x >> 30) & 1
  2218  		if sz == 0 && Q == 0 {
  2219  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2220  		} else if sz == 0 && Q == 1 {
  2221  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2222  		} else if sz == 1 && Q == 1 {
  2223  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2224  		}
  2225  		return nil
  2226  
  2227  	case arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11:
  2228  		Rn := (x >> 5) & (1<<5 - 1)
  2229  		sz := (x >> 22) & 1
  2230  		Q := (x >> 30) & 1
  2231  		if sz == 0 && Q == 0 {
  2232  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2233  		} else if sz == 0 && Q == 1 {
  2234  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2235  		} else if sz == 1 && Q == 0 {
  2236  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2237  		} else /* sz == 1 && Q == 1 */ {
  2238  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2239  		}
  2240  
  2241  	case arg_Vt_1_arrangement_B_index__Q_S_size_1:
  2242  		Rt := x & (1<<5 - 1)
  2243  		Q := (x >> 30) & 1
  2244  		S := (x >> 12) & 1
  2245  		size := (x >> 10) & 3
  2246  		index := (Q << 3) | (S << 2) | (size)
  2247  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 1}
  2248  
  2249  	case arg_Vt_1_arrangement_D_index__Q_1:
  2250  		Rt := x & (1<<5 - 1)
  2251  		index := (x >> 30) & 1
  2252  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 1}
  2253  
  2254  	case arg_Vt_1_arrangement_H_index__Q_S_size_1:
  2255  		Rt := x & (1<<5 - 1)
  2256  		Q := (x >> 30) & 1
  2257  		S := (x >> 12) & 1
  2258  		size := (x >> 11) & 1
  2259  		index := (Q << 2) | (S << 1) | (size)
  2260  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 1}
  2261  
  2262  	case arg_Vt_1_arrangement_S_index__Q_S_1:
  2263  		Rt := x & (1<<5 - 1)
  2264  		Q := (x >> 30) & 1
  2265  		S := (x >> 12) & 1
  2266  		index := (Q << 1) | S
  2267  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 1}
  2268  
  2269  	case arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2270  		Rt := x & (1<<5 - 1)
  2271  		Q := (x >> 30) & 1
  2272  		size := (x >> 10) & 3
  2273  		if size == 0 && Q == 0 {
  2274  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 1}
  2275  		} else if size == 0 && Q == 1 {
  2276  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 1}
  2277  		} else if size == 1 && Q == 0 {
  2278  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 1}
  2279  		} else if size == 1 && Q == 1 {
  2280  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 1}
  2281  		} else if size == 2 && Q == 0 {
  2282  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 1}
  2283  		} else if size == 2 && Q == 1 {
  2284  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 1}
  2285  		} else if size == 3 && Q == 0 {
  2286  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 1}
  2287  		} else /* size == 3 && Q == 1 */ {
  2288  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 1}
  2289  		}
  2290  
  2291  	case arg_Vt_2_arrangement_B_index__Q_S_size_1:
  2292  		Rt := x & (1<<5 - 1)
  2293  		Q := (x >> 30) & 1
  2294  		S := (x >> 12) & 1
  2295  		size := (x >> 10) & 3
  2296  		index := (Q << 3) | (S << 2) | (size)
  2297  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 2}
  2298  
  2299  	case arg_Vt_2_arrangement_D_index__Q_1:
  2300  		Rt := x & (1<<5 - 1)
  2301  		index := (x >> 30) & 1
  2302  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 2}
  2303  
  2304  	case arg_Vt_2_arrangement_H_index__Q_S_size_1:
  2305  		Rt := x & (1<<5 - 1)
  2306  		Q := (x >> 30) & 1
  2307  		S := (x >> 12) & 1
  2308  		size := (x >> 11) & 1
  2309  		index := (Q << 2) | (S << 1) | (size)
  2310  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 2}
  2311  
  2312  	case arg_Vt_2_arrangement_S_index__Q_S_1:
  2313  		Rt := x & (1<<5 - 1)
  2314  		Q := (x >> 30) & 1
  2315  		S := (x >> 12) & 1
  2316  		index := (Q << 1) | S
  2317  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 2}
  2318  
  2319  	case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2320  		Rt := x & (1<<5 - 1)
  2321  		Q := (x >> 30) & 1
  2322  		size := (x >> 10) & 3
  2323  		if size == 0 && Q == 0 {
  2324  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2}
  2325  		} else if size == 0 && Q == 1 {
  2326  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2}
  2327  		} else if size == 1 && Q == 0 {
  2328  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2}
  2329  		} else if size == 1 && Q == 1 {
  2330  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2}
  2331  		} else if size == 2 && Q == 0 {
  2332  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2}
  2333  		} else if size == 2 && Q == 1 {
  2334  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2}
  2335  		} else if size == 3 && Q == 0 {
  2336  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 2}
  2337  		} else /* size == 3 && Q == 1 */ {
  2338  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2}
  2339  		}
  2340  
  2341  	case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2342  		Rt := x & (1<<5 - 1)
  2343  		Q := (x >> 30) & 1
  2344  		size := (x >> 10) & 3
  2345  		if size == 0 && Q == 0 {
  2346  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2}
  2347  		} else if size == 0 && Q == 1 {
  2348  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2}
  2349  		} else if size == 1 && Q == 0 {
  2350  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2}
  2351  		} else if size == 1 && Q == 1 {
  2352  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2}
  2353  		} else if size == 2 && Q == 0 {
  2354  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2}
  2355  		} else if size == 2 && Q == 1 {
  2356  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2}
  2357  		} else if size == 3 && Q == 1 {
  2358  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2}
  2359  		}
  2360  		return nil
  2361  
  2362  	case arg_Vt_3_arrangement_B_index__Q_S_size_1:
  2363  		Rt := x & (1<<5 - 1)
  2364  		Q := (x >> 30) & 1
  2365  		S := (x >> 12) & 1
  2366  		size := (x >> 10) & 3
  2367  		index := (Q << 3) | (S << 2) | (size)
  2368  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 3}
  2369  
  2370  	case arg_Vt_3_arrangement_D_index__Q_1:
  2371  		Rt := x & (1<<5 - 1)
  2372  		index := (x >> 30) & 1
  2373  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 3}
  2374  
  2375  	case arg_Vt_3_arrangement_H_index__Q_S_size_1:
  2376  		Rt := x & (1<<5 - 1)
  2377  		Q := (x >> 30) & 1
  2378  		S := (x >> 12) & 1
  2379  		size := (x >> 11) & 1
  2380  		index := (Q << 2) | (S << 1) | (size)
  2381  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 3}
  2382  
  2383  	case arg_Vt_3_arrangement_S_index__Q_S_1:
  2384  		Rt := x & (1<<5 - 1)
  2385  		Q := (x >> 30) & 1
  2386  		S := (x >> 12) & 1
  2387  		index := (Q << 1) | S
  2388  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 3}
  2389  
  2390  	case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2391  		Rt := x & (1<<5 - 1)
  2392  		Q := (x >> 30) & 1
  2393  		size := (x >> 10) & 3
  2394  		if size == 0 && Q == 0 {
  2395  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3}
  2396  		} else if size == 0 && Q == 1 {
  2397  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3}
  2398  		} else if size == 1 && Q == 0 {
  2399  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3}
  2400  		} else if size == 1 && Q == 1 {
  2401  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3}
  2402  		} else if size == 2 && Q == 0 {
  2403  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3}
  2404  		} else if size == 2 && Q == 1 {
  2405  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3}
  2406  		} else if size == 3 && Q == 0 {
  2407  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 3}
  2408  		} else /* size == 3 && Q == 1 */ {
  2409  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3}
  2410  		}
  2411  
  2412  	case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2413  		Rt := x & (1<<5 - 1)
  2414  		Q := (x >> 30) & 1
  2415  		size := (x >> 10) & 3
  2416  		if size == 0 && Q == 0 {
  2417  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3}
  2418  		} else if size == 0 && Q == 1 {
  2419  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3}
  2420  		} else if size == 1 && Q == 0 {
  2421  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3}
  2422  		} else if size == 1 && Q == 1 {
  2423  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3}
  2424  		} else if size == 2 && Q == 0 {
  2425  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3}
  2426  		} else if size == 2 && Q == 1 {
  2427  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3}
  2428  		} else if size == 3 && Q == 1 {
  2429  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3}
  2430  		}
  2431  		return nil
  2432  
  2433  	case arg_Vt_4_arrangement_B_index__Q_S_size_1:
  2434  		Rt := x & (1<<5 - 1)
  2435  		Q := (x >> 30) & 1
  2436  		S := (x >> 12) & 1
  2437  		size := (x >> 10) & 3
  2438  		index := (Q << 3) | (S << 2) | (size)
  2439  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 4}
  2440  
  2441  	case arg_Vt_4_arrangement_D_index__Q_1:
  2442  		Rt := x & (1<<5 - 1)
  2443  		index := (x >> 30) & 1
  2444  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 4}
  2445  
  2446  	case arg_Vt_4_arrangement_H_index__Q_S_size_1:
  2447  		Rt := x & (1<<5 - 1)
  2448  		Q := (x >> 30) & 1
  2449  		S := (x >> 12) & 1
  2450  		size := (x >> 11) & 1
  2451  		index := (Q << 2) | (S << 1) | (size)
  2452  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 4}
  2453  
  2454  	case arg_Vt_4_arrangement_S_index__Q_S_1:
  2455  		Rt := x & (1<<5 - 1)
  2456  		Q := (x >> 30) & 1
  2457  		S := (x >> 12) & 1
  2458  		index := (Q << 1) | S
  2459  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 4}
  2460  
  2461  	case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2462  		Rt := x & (1<<5 - 1)
  2463  		Q := (x >> 30) & 1
  2464  		size := (x >> 10) & 3
  2465  		if size == 0 && Q == 0 {
  2466  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4}
  2467  		} else if size == 0 && Q == 1 {
  2468  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4}
  2469  		} else if size == 1 && Q == 0 {
  2470  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4}
  2471  		} else if size == 1 && Q == 1 {
  2472  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4}
  2473  		} else if size == 2 && Q == 0 {
  2474  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4}
  2475  		} else if size == 2 && Q == 1 {
  2476  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4}
  2477  		} else if size == 3 && Q == 0 {
  2478  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 4}
  2479  		} else /* size == 3 && Q == 1 */ {
  2480  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4}
  2481  		}
  2482  
  2483  	case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2484  		Rt := x & (1<<5 - 1)
  2485  		Q := (x >> 30) & 1
  2486  		size := (x >> 10) & 3
  2487  		if size == 0 && Q == 0 {
  2488  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4}
  2489  		} else if size == 0 && Q == 1 {
  2490  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4}
  2491  		} else if size == 1 && Q == 0 {
  2492  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4}
  2493  		} else if size == 1 && Q == 1 {
  2494  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4}
  2495  		} else if size == 2 && Q == 0 {
  2496  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4}
  2497  		} else if size == 2 && Q == 1 {
  2498  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4}
  2499  		} else if size == 3 && Q == 1 {
  2500  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4}
  2501  		}
  2502  		return nil
  2503  
  2504  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1:
  2505  		return handle_MemExtend(x, 4, false)
  2506  
  2507  	case arg_Xns_mem_offset:
  2508  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2509  		return MemImmediate{Rn, AddrOffset, 0}
  2510  
  2511  	case arg_Xns_mem_optional_imm12_16_unsigned:
  2512  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2513  		imm12 := (x >> 10) & (1<<12 - 1)
  2514  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 4)}
  2515  
  2516  	case arg_Xns_mem_optional_imm7_16_signed:
  2517  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2518  		imm7 := (x >> 15) & (1<<7 - 1)
  2519  		return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 4)) << 21) >> 21}
  2520  
  2521  	case arg_Xns_mem_post_fixedimm_1:
  2522  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2523  		return MemImmediate{Rn, AddrPostIndex, 1}
  2524  
  2525  	case arg_Xns_mem_post_fixedimm_12:
  2526  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2527  		return MemImmediate{Rn, AddrPostIndex, 12}
  2528  
  2529  	case arg_Xns_mem_post_fixedimm_16:
  2530  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2531  		return MemImmediate{Rn, AddrPostIndex, 16}
  2532  
  2533  	case arg_Xns_mem_post_fixedimm_2:
  2534  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2535  		return MemImmediate{Rn, AddrPostIndex, 2}
  2536  
  2537  	case arg_Xns_mem_post_fixedimm_24:
  2538  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2539  		return MemImmediate{Rn, AddrPostIndex, 24}
  2540  
  2541  	case arg_Xns_mem_post_fixedimm_3:
  2542  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2543  		return MemImmediate{Rn, AddrPostIndex, 3}
  2544  
  2545  	case arg_Xns_mem_post_fixedimm_32:
  2546  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2547  		return MemImmediate{Rn, AddrPostIndex, 32}
  2548  
  2549  	case arg_Xns_mem_post_fixedimm_4:
  2550  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2551  		return MemImmediate{Rn, AddrPostIndex, 4}
  2552  
  2553  	case arg_Xns_mem_post_fixedimm_6:
  2554  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2555  		return MemImmediate{Rn, AddrPostIndex, 6}
  2556  
  2557  	case arg_Xns_mem_post_fixedimm_8:
  2558  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2559  		return MemImmediate{Rn, AddrPostIndex, 8}
  2560  
  2561  	case arg_Xns_mem_post_imm7_16_signed:
  2562  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2563  		imm7 := (x >> 15) & (1<<7 - 1)
  2564  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 4)) << 21) >> 21}
  2565  
  2566  	case arg_Xns_mem_post_Q__16_0__32_1:
  2567  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2568  		Q := (x >> 30) & 1
  2569  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 16)}
  2570  
  2571  	case arg_Xns_mem_post_Q__24_0__48_1:
  2572  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2573  		Q := (x >> 30) & 1
  2574  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 24)}
  2575  
  2576  	case arg_Xns_mem_post_Q__32_0__64_1:
  2577  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2578  		Q := (x >> 30) & 1
  2579  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 32)}
  2580  
  2581  	case arg_Xns_mem_post_Q__8_0__16_1:
  2582  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2583  		Q := (x >> 30) & 1
  2584  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 8)}
  2585  
  2586  	case arg_Xns_mem_post_size__1_0__2_1__4_2__8_3:
  2587  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2588  		size := (x >> 10) & 3
  2589  		return MemImmediate{Rn, AddrPostIndex, int32(1 << size)}
  2590  
  2591  	case arg_Xns_mem_post_size__2_0__4_1__8_2__16_3:
  2592  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2593  		size := (x >> 10) & 3
  2594  		return MemImmediate{Rn, AddrPostIndex, int32(2 << size)}
  2595  
  2596  	case arg_Xns_mem_post_size__3_0__6_1__12_2__24_3:
  2597  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2598  		size := (x >> 10) & 3
  2599  		return MemImmediate{Rn, AddrPostIndex, int32(3 << size)}
  2600  
  2601  	case arg_Xns_mem_post_size__4_0__8_1__16_2__32_3:
  2602  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2603  		size := (x >> 10) & 3
  2604  		return MemImmediate{Rn, AddrPostIndex, int32(4 << size)}
  2605  
  2606  	case arg_Xns_mem_post_Xm:
  2607  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2608  		Rm := (x >> 16) & (1<<5 - 1)
  2609  		return MemImmediate{Rn, AddrPostReg, int32(Rm)}
  2610  
  2611  	case arg_Xns_mem_wb_imm7_16_signed:
  2612  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2613  		imm7 := (x >> 15) & (1<<7 - 1)
  2614  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 4)) << 21) >> 21}
  2615  	}
  2616  }
  2617  
  2618  func handle_ExtendedRegister(x uint32, has_width bool) Arg {
  2619  	s := (x >> 29) & 1
  2620  	rm := (x >> 16) & (1<<5 - 1)
  2621  	option := (x >> 13) & (1<<3 - 1)
  2622  	imm3 := (x >> 10) & (1<<3 - 1)
  2623  	rn := (x >> 5) & (1<<5 - 1)
  2624  	rd := x & (1<<5 - 1)
  2625  	is_32bit := !has_width
  2626  	var rea RegExtshiftAmount
  2627  	if has_width {
  2628  		if option&0x3 != 0x3 {
  2629  			rea.reg = W0 + Reg(rm)
  2630  		} else {
  2631  			rea.reg = X0 + Reg(rm)
  2632  		}
  2633  	} else {
  2634  		rea.reg = W0 + Reg(rm)
  2635  	}
  2636  	switch option {
  2637  	case 0:
  2638  		rea.extShift = uxtb
  2639  	case 1:
  2640  		rea.extShift = uxth
  2641  	case 2:
  2642  		if is_32bit && (rn == 31 || (s == 0 && rd == 31)) {
  2643  			if imm3 != 0 {
  2644  				rea.extShift = lsl
  2645  			} else {
  2646  				rea.extShift = ExtShift(0)
  2647  			}
  2648  		} else {
  2649  			rea.extShift = uxtw
  2650  		}
  2651  	case 3:
  2652  		if !is_32bit && (rn == 31 || (s == 0 && rd == 31)) {
  2653  			if imm3 != 0 {
  2654  				rea.extShift = lsl
  2655  			} else {
  2656  				rea.extShift = ExtShift(0)
  2657  			}
  2658  		} else {
  2659  			rea.extShift = uxtx
  2660  		}
  2661  	case 4:
  2662  		rea.extShift = sxtb
  2663  	case 5:
  2664  		rea.extShift = sxth
  2665  	case 6:
  2666  		rea.extShift = sxtw
  2667  	case 7:
  2668  		rea.extShift = sxtx
  2669  	}
  2670  	rea.show_zero = false
  2671  	rea.amount = uint8(imm3)
  2672  	return rea
  2673  }
  2674  
  2675  func handle_ImmediateShiftedRegister(x uint32, max uint8, is_w, has_ror bool) Arg {
  2676  	var rsa RegExtshiftAmount
  2677  	if is_w {
  2678  		rsa.reg = W0 + Reg((x>>16)&(1<<5-1))
  2679  	} else {
  2680  		rsa.reg = X0 + Reg((x>>16)&(1<<5-1))
  2681  	}
  2682  	switch (x >> 22) & 0x3 {
  2683  	case 0:
  2684  		rsa.extShift = lsl
  2685  	case 1:
  2686  		rsa.extShift = lsr
  2687  	case 2:
  2688  		rsa.extShift = asr
  2689  	case 3:
  2690  		if has_ror {
  2691  			rsa.extShift = ror
  2692  		} else {
  2693  			return nil
  2694  		}
  2695  	}
  2696  	rsa.show_zero = true
  2697  	rsa.amount = uint8((x >> 10) & (1<<6 - 1))
  2698  	if rsa.amount == 0 && rsa.extShift == lsl {
  2699  		rsa.extShift = ExtShift(0)
  2700  	} else if rsa.amount > max {
  2701  		return nil
  2702  	}
  2703  	return rsa
  2704  }
  2705  
  2706  func handle_MemExtend(x uint32, mult uint8, absent bool) Arg {
  2707  	var extend ExtShift
  2708  	var Rm Reg
  2709  	option := (x >> 13) & (1<<3 - 1)
  2710  	Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2711  	if (option & 1) != 0 {
  2712  		Rm = Reg(X0) + Reg(x>>16&(1<<5-1))
  2713  	} else {
  2714  		Rm = Reg(W0) + Reg(x>>16&(1<<5-1))
  2715  	}
  2716  	switch option {
  2717  	default:
  2718  		return nil
  2719  	case 2:
  2720  		extend = uxtw
  2721  	case 3:
  2722  		extend = lsl
  2723  	case 6:
  2724  		extend = sxtw
  2725  	case 7:
  2726  		extend = sxtx
  2727  	}
  2728  	amount := (uint8((x >> 12) & 1)) * mult
  2729  	return MemExtend{Rn, Rm, extend, amount, absent}
  2730  }
  2731  
  2732  func handle_bitmasks(x uint32, datasize uint8) Arg {
  2733  	var length, levels, esize, i uint8
  2734  	var welem, wmask uint64
  2735  	n := (x >> 22) & 1
  2736  	imms := uint8((x >> 10) & (1<<6 - 1))
  2737  	immr := uint8((x >> 16) & (1<<6 - 1))
  2738  	if n != 0 {
  2739  		length = 6
  2740  	} else if (imms & 32) == 0 {
  2741  		length = 5
  2742  	} else if (imms & 16) == 0 {
  2743  		length = 4
  2744  	} else if (imms & 8) == 0 {
  2745  		length = 3
  2746  	} else if (imms & 4) == 0 {
  2747  		length = 2
  2748  	} else if (imms & 2) == 0 {
  2749  		length = 1
  2750  	} else {
  2751  		return nil
  2752  	}
  2753  	levels = 1<<length - 1
  2754  	s := imms & levels
  2755  	r := immr & levels
  2756  	esize = 1 << length
  2757  	if esize > datasize {
  2758  		return nil
  2759  	}
  2760  	welem = 1<<(s+1) - 1
  2761  	ror := (welem >> r) | (welem << (esize - r))
  2762  	ror &= ((1 << esize) - 1)
  2763  	wmask = 0
  2764  	for i = 0; i < datasize; i += esize {
  2765  		wmask = (wmask << esize) | ror
  2766  	}
  2767  	return Imm64{wmask, false}
  2768  }
  2769  

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